The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 µm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 £gm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.