Le domaine de la recherche dans les multi-standards, les systèmes multi-bandes, architectures, et circuits a été un thème populaire. La perspective est d'avoir des dispositifs qui peuvent être adaptés, parfaitement, aux différents réseaux tout en offrant d'excellentes fonctionnalités sur les différents technologies d’accès radio. Les architectures de transmetteurs configurables ciblant les cas d'utilisation complémentaires des WiFi-WiGig ont été étudiés. Des approches novatrices basées sur des DAC FIR semi-numériques configurables à grande vitesse sont proposées. Les DAC de FIR nécessitent des filtres longs avec des coefficients de résolution élevés pour atteindre des niveaux d'atténuation de stopband satisfaisants aux exigences de bruit hors bande. Normalement, cela limite la vitesse et se traduit par une grande surface de silicium. Dans ce travail, les techniques de conception de circuits sont développées de sorte qu'un élément de circuit unitaire réalisant un coefficient d'une fonction de transfert peut être réutilisé dans la réalisation d’un coefficient d'une autre fonction de transfert. Une puce prototype de passe-haut FIR DAC qui peut être configuré pour le fonctionnement de l'IEEE 802.11ac et les standards IEEE 802.11ad a été mise en œuvre sur une technologie CMOS 28nm FDSOI de STMicroelectronics. Le test De cette puce a démontré la validité des architectures d'émetteur proposées. Le puce prototype peut traiter des signaux des bandes de base aussi larges que 63,63 MHz et 300 MHz à une fréquence d'horloge de 1,4 GHz avec une consommation de 103,07 mW dans le 802.11ac et 86,89 mW dans le mode 802.11ad. / The vision of research into multi-standard and multi-band systems, architectures, and circuits has been to develop devices which can hope seamlessly from one network to the other while delivering excellent functionality in different radio access technologies.In this work, configurable transmitter architectures based on FIR DACs which target WiFi-WiGig complementary use cases have been studied. FIR DACs require long filters with high resolution coefficients to meet high out-of-band noise attenuation. Normally, this limits speed and results in large area. In this work, circuit techniques are developed so that a unit circuit element realizing a coefficient of one transfer function can be re-used in realizing a different-valued coefficient of another transfer function. The work also proposes topologies that exploit digital signal processing at advanced nodes to implement quadrature modulation while realizing up-conversion, digital-to-analog conversion and image and quantization filtering in one configurable FIR DAC block. A prototype high pass FIR DAC chip which can be configured for processing IEEE 802.11ac and IEEE 802.11ad signals was implemented in ST CMOS 28nm FDSOI technology. The test of this chip has demonstrated the validity of the proposed transmitter architectures. The prototype chip can process baseband signals as wide as 63.63 MHz and 300 MHz at a clock frequency of 1.4 GHz while consuming 103.07 mW in the 802.11ac and 86.89 mW in the 802.11ad modes.

This thesis focuses on the design and analysis of a novel variable inductor (VID) based VCO solution to the frequency tuning range (TR) limitation of the IEEE 802.11ad compliant radio systems. The IEEE 802.11ad standard has drawn strong attention from the industry as the next generation affordable multi-gigabit speed wireless communication standard. Prepared for the global market, IEEE 802.11ad compliant systems are required to cover a broad 8 GHz TR centered on 60 GHz. This wide TR at V band imposes significant challenge to the VCO design in radio transceivers, and makes the TR of the integrated VCO a major bottleneck to the successful commercialization of many IEEE 802.11ad compliant radio systems today. As an effort to solve the current TR problem for the IEEE 802.11ad compliant radio systems, 2 VCOs designs based on this novel VID-based solution and a conventional Colpitts-Clapp VCO design are presented in this thesis report. The novel VCOs integrate a VID into the differential Colpitts configuration to create a feasible solution to the aforementioned TR problem. The VID in the VCO tank eliminates the base node varactors and their fixed parasitic capacitance that degrades TR in conventional VCO designs, while the differential Colpitts configuration provides advantageous performance at mm-wave frequencies and high output power for real-world applications. Also, a fundamental 30 GHz Colpitts-Clapp VCO was developed in conjunction with the other 2 VCOs for comparison purposes. One of the 2 VID-based VCO designs is a fundamental 30 GHz VID-based Colpitts VCO that covers 17% TR for proof of concept to the novel topology. Another is an IEEE 802.11ad compliant 60 GHz VCO chain consists of the 30 GHz VID-based Colpitts VCO and a frequency doubler covering 17% TR with 3 dBm output power and -115.7 dBc/Hz phase noise at 10 MHz offset. The conventional Colpitts-Clapp VCO is used to compare with the other 2 VID-based VCOs. As the measurement results indicate, this VID-based VCO topology provides a viable solution to overcome the TR bottleneck in the current IEEE 802.11ad compliant VCO development. All 3 VCOs are fabricated using a 130 nm SiGe BiCMOS process. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2014-01-23 13:40:31.258

abstract: ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps. / Dissertation/Thesis / M.S. Electrical Engineering 2010