This thesis presents a novel VLSI design of multi-code rate Low-Density Parity-Check code (LDPC) decoder for IEEE 802.16e standard. In order to support the different code rates adopted by the standard, this thesis proposes a programmable LDPC decoder architecture based on the edge-serial approach. This edge-serial architecture can perform the sequential check-node computation according to the internal sequence update commands. Any complex and irregular parity-check matrix can all be realized in the proposed architecture if the number of bit-nodes each check node connects does not exceed a certain bound. In addition to the high flexibility, this thesis also proposes several design optimization techniques suitable for the LDPC decoder. First, the designs of the LDPC decoders in the past all put more emphasis on the realization of check node function. This thesis instead applies a novel bit-node major approach which can lead to more compact design. Secondly, a fine-grain message update method is used which allows more rapid message passing such that the decoder can converge in less cycles. In addition, almost half of the message memory can be reduced. Furthermore, based on the bit-node major decoder design, the early termination scheme can be utilized to partially terminate the function of some bit nodes to reduce the decoding cycles. The other salient features also include the rescheduling of the message update order to allow the overlap of different decoding iterations in order to reduce effect of the possible message update hazard due to the long internal pipeline latency. Based on the proposed optimization methods, our experimental results show that the hardware cost can be reduced by 23.1% while the decoding cycles can be reduced by 27.4%. The proposed LDPC decoder architecture has been realized by using 0.18 µm technology with the total gate count of 316k. Our experimental shows that the proposed LDPC decoder can run up to 235 MHz and deliver the average of 116 Mbps throughput.