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Reduced-order modelling, circuit-level design and SOI fabrication of microelectromechanical resonatorsdel Tin, Laura <1979> 27 March 2007 (has links)
This thesis deals with two important research aspects concerning radio frequency (RF) microresonators and switches. First, a new approach for compact modeling and simulation of these devices is presented. Then, a combined process flow for their simultaneous fabrication on a SOI
substrate is proposed. Compact models for microresonators and switches are extracted by applying mathematical model
order reduction (MOR) to the devices finite element (FE) description in ANSYS c° . The behaviour of these devices includes forms of nonlinearities. However, an approximation in the creation of the FE model is introduced, which enables the use of linear model order reduction. Microresonators are modeled with the introduction of transducer elements, which allow for direct coupling of the electrical and mechanical domain. The coupled system element matrices are linearized around an operating point and reduced. The resulting macromodel is valid for small signal analysis around the bias point, such as harmonic pre-stressed analysis. This is extremely useful for characterizing the frequency response of resonators. Compact modelling of switches preserves the nonlinearity of the device behaviour. Nonlinear reduced order models are obtained by reducing the number of nonlinearities in the system and handling them as input to the system. In this way, the system can be reduced using linear MOR techniques and nonlinearities are introduced directly in the reduced order model. The reduction of the number of system nonlinearities implies the approximation of all distributed forces in the model with lumped forces. Both for microresonators and switches, a procedure for matrices extraction has been developed so that reduced order models include the effects of electrical and mechanical pre-stress. The extraction process is fast and can be done automatically from ANSYS binary files. The method has been applied for the simulation of several devices both at devices and circuit
level. Simulation results have been compared with full model simulations, and, when available, experimental data. Reduced order models have proven to conserve the accuracy of finite element method and to give a good description of the overall device behaviour, despite the introduced approximations. In addition, simulation is very fast, both at device and circuit level. A combined process-flow for the integrated fabrication of microresonators and switches has been defined. For this purpose, two processes that are optimized for the independent fabrication of these devices are merged. The major advantage of this process is the possibility to create on-chip circuit blocks that include both microresonators and switches. An application is, for example, aswitched filter bank for wireless transceiver. The process for microresonators fabrication is characterized by the use of silicon on insulator (SOI) wafers and on a deep reactive ion etching (DRIE) step for the creation of the vibrating structures in single-crystal silicon and the use of a sacrificial oxide layer for the definition of resonator to electrode distance. The fabrication of switches is characterized by the use of two different conductive layers for the definition of the actuation electrodes and by the use of a photoresist as a sacrificial layer for the creation of the suspended structure. Both processes have a gold electroplating step, for the creation of the resonators electrodes, transmission lines and suspended structures. The combined process flow is designed such that it conserves the basic properties of the original processes. Neither the performance of the resonators nor the performance of the switches results affected by the simultaneous fabrication. Moreover, common fabrication steps are shared, which allows for cheaper and faster fabrication.
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Modelling and characterization of decananometric electronic devicesEminente, Simone <1978> 30 March 2007 (has links)
No description available.
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Mixed-domain simulation and hybrid wafer-level packaging of RF-MEMS devices for wireless applicationsIannacci, Jacopo <1977> 27 March 2007 (has links)
In questa tesi verranno trattati sia il problema della creazione di un ambiente di simulazione a domini fisici misti per dispositivi RF-MEMS, che la definizione di un processo di fabbricazione ad-hoc per il packaging e l’integrazione degli stessi. Riguardo al primo argomento, sarà mostrato nel dettaglio lo sviluppo di una libreria di modelli MEMS all’interno dell’ambiente di simulazione per circuiti integrati Cadence c . L’approccio scelto per la definizione del comportamento elettromeccanico dei MEMS è basato sul concetto di modellazione compatta (compact modeling). Questo significa che il comportamento fisico di ogni componente elementare della libreria è descritto per mezzo di un insieme limitato di punti (nodi) di interconnessione verso il mondo esterno. La libreria comprende componenti elementari, come travi flessibili, piatti rigidi sospesi e punti di ancoraggio, la cui opportuna interconnessione porta alla realizzazione di interi dispositivi (come interruttori e capacità variabili) da simulare in Cadence c . Tutti i modelli MEMS sono implementati per mezzo del linguaggio VerilogA c di tipo HDL (Hardware Description Language) che è supportato dal simulatore circuitale Spectre c . Sia il linguaggio VerilogA
c che il simulatore Spectre c sono disponibili in ambiente Cadence c . L’ambiente di simulazione multidominio (ovvero elettromeccanico) così ottenuto permette di interfacciare i
dispositivi MEMS con le librerie di componenti CMOS standard e di conseguenza la simulazione di blocchi funzionali misti RF-MEMS/CMOS. Come esempio, un VCO (Voltage Controlled Oscillator) in cui l’LC-tank è realizzato in tecnologia MEMS mentre la parte attiva con transistor MOS di libreria sarà
simulato in Spectre c . Inoltre, nelle pagine successive verrà mostrata una soluzione tecnologica per la fabbricazione di un substrato protettivo (package) da applicare a dispositivi RF-MEMS basata su vie di interconnessione elettrica attraverso un wafer di Silicio. La soluzione di packaging prescelta rende possibili alcune tecniche per l’integrazione ibrida delle parti RF-MEMS e CMOS (hybrid packaging). Verranno inoltre messe in luce questioni riguardanti gli effetti parassiti (accoppiamenti
capacitivi ed induttivi) introdotti dal package che influenzano le prestazioni RF dei dispositivi MEMS incapsulati. Nel dettaglio, tutti i gradi di libertà del processo tecnologico per l’ottenimento del package saranno ottimizzati per mezzo di un simulatore elettromagnetico (Ansoft HFSSTM) al fine di ridurre gli effetti parassiti introdotti dal substrato protettivo. Inoltre, risultati sperimentali raccolti da misure di strutture di test incapsulate verranno mostrati per validare, da un lato, il simulatore Ansoft HFSSTM e per dimostrate, dall’altro, la fattibilit`a della soluzione di packaging proposta. Aldilà dell’apparente debole legame tra i due argomenti sopra menzionati è possibile identificare un unico obiettivo. Da un lato questo è da ricercarsi nello sviluppo di un ambiente di simulazione unificato all’interno del quale il comportamento elettromeccanico dei dispositivi RF-MEMS possa essere studiato ed analizzato. All’interno di tale ambiente, l’influenza del package sul comportamento elettromagnetico degli RF-MEMS può essere tenuta in conto per mezzo di modelli a parametri concentrati (lumped elements) estratti da misure sperimentali e simulazioni agli Elementi Finiti (FEM) della parte di package. Infine, la possibilità offerta dall’ambiente Cadence c relativamente alla simulazione di dipositivi RF-MEMS interfacciati alla parte CMOS rende
possibile l’analisi di blocchi funzionali ibridi RF-MEMS/CMOS completi.
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Chaos-based random number generators: monolithic implementation, testing and applicationsPareschi, Fabio <1976> 26 March 2007 (has links)
No description available.
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Models and methods for power monolithic microwave integrated circuitsResca, Davide <1979> 17 April 2008 (has links)
Computer aided design of Monolithic Microwave Integrated Circuits (MMICs) depends
critically on active device models that are accurate, computationally efficient, and easily extracted
from measurements or device simulators.
Empirical models of active electron devices, which are based on actual device measurements, do
not provide a detailed description of the electron device physics. However they are numerically
efficient and quite accurate. These characteristics make them very suitable for MMIC design in the
framework of commercially available CAD tools.
In the empirical model formulation it is very important to separate linear memory effects
(parasitic effects) from the nonlinear effects (intrinsic effects). Thus an empirical active device
model is generally described by an extrinsic linear part which accounts for the parasitic passive
structures connecting the nonlinear intrinsic electron device to the external world.
An important task circuit designers deal with is evaluating the ultimate potential of a device for
specific applications. In fact once the technology has been selected, the designer would choose the
best device for the particular application and the best device for the different blocks composing the
overall MMIC. Thus in order to accurately reproducing the behaviour of different-in-size devices,
good scalability properties of the model are necessarily required.
Another important aspect of empirical modelling of electron devices is the mathematical (or
equivalent circuit) description of the nonlinearities inherently associated with the intrinsic device.
Once the model has been defined, the proper measurements for the characterization of the device
are performed in order to identify the model. Hence, the correct measurement of the device
nonlinear characteristics (in the device characterization phase) and their reconstruction (in the
identification or even simulation phase) are two of the more important aspects of empirical
modelling.
This thesis presents an original contribution to nonlinear electron device empirical modelling
treating the issues of model scalability and reconstruction of the device nonlinear characteristics.
The scalability of an empirical model strictly depends on the scalability of the linear extrinsic
parasitic network, which should possibly maintain the link between technological process
parameters and the corresponding device electrical response.
Since lumped parasitic networks, together with simple linear scaling rules, cannot provide
accurate scalable models, either complicate technology-dependent scaling rules or computationally
inefficient distributed models are available in literature.
This thesis shows how the above mentioned problems can be avoided through the use of
commercially available electromagnetic (EM) simulators. They enable the actual device geometry
and material stratification, as well as losses in the dielectrics and electrodes, to be taken into
account for any given device structure and size, providing an accurate description of the parasitic
effects which occur in the device passive structure. It is shown how the electron device behaviour
can be described as an equivalent two-port intrinsic nonlinear block connected to a linear distributed
four-port passive parasitic network, which is identified by means of the EM simulation of the device
layout, allowing for better frequency extrapolation and scalability properties than conventional
empirical models.
Concerning the issue of the reconstruction of the nonlinear electron device characteristics, a data
approximation algorithm has been developed for the exploitation in the framework of empirical
table look-up nonlinear models. Such an approach is based on the strong analogy between timedomain
signal reconstruction from a set of samples and the continuous approximation of device
nonlinear characteristics on the basis of a finite grid of measurements. According to this criterion,
nonlinear empirical device modelling can be carried out by using, in the sampled voltage domain,
typical methods of the time-domain sampling theory.
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Tecniche per il controllo dinamico del consumo di potenza per piattaforme system-on-chipRuggiero, Martino <1979> 17 April 2008 (has links)
Providing support for multimedia applications on low-power mobile devices
remains a significant research challenge. This is primarily due to two reasons:
• Portable mobile devices have modest sizes and weights, and therefore
inadequate resources, low CPU processing power, reduced display capabilities,
limited memory and battery lifetimes as compared to desktop
and laptop systems.
• On the other hand, multimedia applications tend to have distinctive QoS
and processing requirementswhichmake themextremely resource-demanding.
This innate conflict introduces key research challenges in the design of multimedia
applications and device-level power optimization.
Energy efficiency in this kind of platforms can be achieved only via a synergistic
hardware and software approach. In fact, while System-on-Chips are
more and more programmable thus providing functional flexibility, hardwareonly
power reduction techniques cannot maintain consumption under acceptable
bounds.
It is well understood both in research and industry that system configuration
andmanagement cannot be controlled efficiently only relying on low-level
firmware and hardware drivers. In fact, at this level there is lack of information
about user application activity and consequently about the impact of power
management decision on QoS.
Even though operating system support and integration is a requirement
for effective performance and energy management, more effective and QoSsensitive
power management is possible if power awareness and hardware
configuration control strategies are tightly integratedwith domain-specificmiddleware
services.
The main objective of this PhD research has been the exploration and the
integration of amiddleware-centric energymanagement with applications and
operating-system. We choose to focus on the CPU-memory and the video subsystems,
since they are the most power-hungry components of an embedded
system. A second main objective has been the definition and implementation
of software facilities (like toolkits, API, and run-time engines) in order to improve
programmability and performance efficiency of such platforms.
Enhancing energy efficiency and programmability ofmodernMulti-Processor
System-on-Chips (MPSoCs)
Consumer applications are characterized by tight time-to-market constraints
and extreme cost sensitivity. The software that runs on modern embedded
systems must be high performance, real time, and even more important low
power. Although much progress has been made on these problems, much
remains to be done.
Multi-processor System-on-Chip (MPSoC) are increasingly popular platforms
for high performance embedded applications. This leads to interesting
challenges in software development since efficient software development is a
major issue for MPSoc designers.
An important step in deploying applications on multiprocessors is to allocate
and schedule concurrent tasks to the processing and communication resources
of the platform. The problem of allocating and scheduling precedenceconstrained
tasks on processors in a distributed real-time system is NP-hard.
There is a clear need for deployment technology that addresses thesemulti processing
issues. This problem can be tackled by means of specific middleware
which takes care of allocating and scheduling tasks on the different processing
elements and which tries also to optimize the power consumption of the entire
multiprocessor platform.
This dissertation is an attempt to develop insight into efficient, flexible and
optimalmethods for allocating and scheduling concurrent applications tomultiprocessor
architectures.
It is a well-known problem in literature: this kind of optimization problems
are very complex even in much simplified variants, therefore most authors
propose simplified models and heuristic approaches to solve it in reasonable
time. Model simplification is often achieved by abstracting away platform
implementation ”details”. As a result, optimization problems become more
tractable, even reaching polynomial time complexity. Unfortunately, this approach
creates an abstraction gap between the optimization model and the real
HW-SW platform. The main issue with heuristic or, more in general, with incomplete
search is that they introduce an optimality gap of unknown size. They
provide very limited or no information on the distance between the best computed
solution and the optimal one.
The goal of this work is to address both abstraction and optimality gaps,
formulating accurate models which accounts for a number of ”non-idealities”
in real-life hardware platforms, developing novel mapping algorithms that deterministically
find optimal solutions, and implementing software infrastructures
required by developers to deploy applications for the targetMPSoC platforms.
Energy Efficient LCDBacklightAutoregulation on Real-LifeMultimediaAp-
plication Processor
Despite the ever increasing advances in Liquid Crystal Display’s (LCD) technology,
their power consumption is still one of the major limitations to the battery
life of mobile appliances such as smart phones, portable media players,
gaming and navigation devices. There is a clear trend towards the increase of
LCD size to exploit the multimedia capabilities of portable devices that can receive
and render high definition video and pictures. Multimedia applications
running on these devices require LCD screen sizes of 2.2 to 3.5 inches andmore
to display video sequences and pictures with the required quality.
LCD power consumption is dependent on the backlight and pixel matrix
driving circuits and is typically proportional to the panel area. As a result, the
contribution is also likely to be considerable in future mobile appliances. To
address this issue, companies are proposing low power technologies suitable
for mobile applications supporting low power states and image control techniques.
On the research side, several power saving schemes and algorithms can be
found in literature. Some of them exploit software-only techniques to change
the image content to reduce the power associated with the crystal polarization,
some others are aimed at decreasing the backlight level while compensating
the luminance reduction by compensating the user perceived quality degradation
using pixel-by-pixel image processing algorithms. The major limitation of
these techniques is that they rely on the CPU to perform pixel-based manipulations
and their impact on CPU utilization and power consumption has not
been assessed.
This PhDdissertation shows an alternative approach that exploits in a smart
and efficient way the hardware image processing unit almost integrated in every
current multimedia application processors to implement a hardware assisted
image compensation that allows dynamic scaling of the backlight with
a negligible impact on QoS. The proposed approach overcomes CPU-intensive
techniques by saving system power without requiring either a dedicated display technology or hardware modification.
Thesis Overview
The remainder of the thesis is organized as follows.
The first part is focused on enhancing energy efficiency and programmability
of modern Multi-Processor System-on-Chips (MPSoCs). Chapter 2 gives
an overview about architectural trends in embedded systems, illustrating the
principal features of new technologies and the key challenges still open. Chapter
3 presents a QoS-driven methodology for optimal allocation and frequency
selection for MPSoCs. The methodology is based on functional simulation
and full system power estimation. Chapter 4 targets allocation and scheduling
of pipelined stream-oriented applications on top of distributed memory
architectures with messaging support. We tackled the complexity of the problem
by means of decomposition and no-good generation, and prove the increased
computational efficiency of this approach with respect to traditional
ones. Chapter 5 presents a cooperative framework to solve the allocation,
scheduling and voltage/frequency selection problem to optimality for energyefficient
MPSoCs, while in Chapter 6 applications with conditional task graph
are taken into account. Finally Chapter 7 proposes a complete framework,
called Cellflow, to help programmers in efficient software implementation on
a real architecture, the Cell Broadband Engine processor.
The second part is focused on energy efficient software techniques for LCD
displays. Chapter 8 gives an overview about portable device display technologies,
illustrating the principal features of LCD video systems and the key challenges
still open. Chapter 9 shows several energy efficient software techniques
present in literature, while Chapter 10 illustrates in details our method for saving
significant power in an LCD panel.
Finally, conclusions are drawn, reporting the main research contributions
that have been discussed throughout this dissertation.
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Exploration of communication strategies for computation intensive Systems-On-ChipDeledda, Antonio <1980> 17 April 2008 (has links)
No description available.
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Control of the position of particles in open microfluidic systemsGazzola, Daniele <1976> 17 April 2008 (has links)
No description available.
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Design of wireless sensor networks for fluid dynamic applicationsCodeluppi, Rossano <1974> 17 April 2008 (has links)
In fluid dynamics research, pressure measurements are of great importance to define
the flow field acting on aerodynamic surfaces. In fact the experimental approach is
fundamental to avoid the complexity of the mathematical models for predicting the
fluid phenomena.
It’s important to note that, using in-situ sensor to monitor pressure on large domains
with highly unsteady flows, several problems are encountered working with the
classical techniques due to the transducer cost, the intrusiveness, the time response
and the operating range.
An interesting approach for satisfying the previously reported sensor requirements is
to implement a sensor network capable of acquiring pressure data on aerodynamic
surface using a wireless communication system able to collect the pressure data with
the lowest environmental–invasion level possible.
In this thesis a wireless sensor network for fluid fields pressure has been designed,
built and tested.
To develop the system, a capacitive pressure sensor, based on polymeric membrane,
and read out circuitry, based on microcontroller, have been designed, built and
tested. The wireless communication has been performed using the Zensys Z-WAVE
platform, and network and data management have been implemented. Finally, the
full embedded system with antenna has been created.
As a proof of concept, the monitoring of pressure on the top of the mainsail in a sailboat
has been chosen as working example.
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Interconnection systems for highly integrated computation devicesAngiolini, Federico <1978> 17 April 2008 (has links)
The sustained demand for faster,more powerful chips has beenmet by the
availability of chip manufacturing processes allowing for the integration
of increasing numbers of computation units onto a single die. The resulting
outcome, especially in the embedded domain, has often been called
SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC).
MPSoC design brings to the foreground a large number of challenges,
one of the most prominent of which is the design of the chip interconnection.
With a number of on-chip blocks presently ranging in the tens, and
quickly approaching the hundreds, the novel issue of how to best provide
on-chip communication resources is clearly felt.
NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable
answer to this design concern. By bringing large-scale networking
concepts to the on-chip domain, they guarantee a structured answer to
present and future communication requirements. The point-to-point connection
and packet switching paradigms they involve are also of great help
in minimizing wiring overhead and physical routing issues.
However, as with any technology of recent inception, NoC design is
still an evolving discipline. Several main areas of interest require deep
investigation for NoCs to become viable solutions:
• The design of the NoC architecture needs to strike the best tradeoff
among performance, features and the tight area and power constraints
of the on-chip domain.
• Simulation and verification infrastructure must be put in place to
explore, validate and optimize the NoC performance.
• NoCs offer a huge design space, thanks to their extreme customizability
in terms of topology and architectural parameters. Design
tools are needed to prune this space and pick the best solutions.
• Even more so given their global, distributed nature, it is essential to
evaluate the physical implementation of NoCs to evaluate their suitability
for next-generation designs and their area and power costs.
This dissertation focuses on all of the above points, by describing a
NoC architectural implementation called ×pipes; a NoC simulation environment
within a cycle-accurate MPSoC emulator called MPARM; a NoC
design flow consisting of a front-end tool for optimal NoC instantiation,
called SunFloor, and a set of back-end facilities for the study of NoC physical
implementations.
This dissertation proves the viability of NoCs for current and upcoming
designs, by outlining their advantages (alongwith a fewtradeoffs) and
by providing a full NoC implementation framework. It also presents some
examples of additional extensions of NoCs, allowing e.g. for increased
fault tolerance, and outlines where NoCsmay find further application scenarios,
such as in stacked chips.
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