Graphene, that is a monolayer of carbon atoms arranged in a honeycomb lattice, has been isolated only recently from graphite. This material shows very attractive physical properties, like superior carrier mobility, current carrying capability and thermal conductivity. In consideration of that, graphene has been the object of large investigation as a promising candidate to be used in nanometer-scale devices for electronic applications. In this work, graphene nanoribbons (GNRs), that are narrow strips of graphene, for which a band-gap is induced by the quantum confinement of carriers in the transverse direction, have been studied. As experimental GNR-FETs are still far from being ideal, mainly due to the large width and edge roughness, an accurate description of the physical phenomena occurring in these devices is required to have valuable predictions about the performance of these novel structures. A code has been developed to this purpose and used to investigate the performance of 1 to 15-nm wide GNR-FETs. Due to the importance of an accurate description of the quantum effects in the operation of graphene devices, a full-quantum transport model has been adopted: the electron dynamics has been described by a tight-binding (TB) Hamiltonian model and transport has been solved within the formalism of the non-equilibrium Green's functions (NEGF). Both ballistic and dissipative transport are considered. The inclusion of the electron-phonon interaction has been taken into account in the self-consistent Born approximation. In consideration of their different energy band-gap, narrow GNRs are expected to be suitable for logic applications, while wider ones could be promising candidates as channel material for radio-frequency applications.

Thermal effects are rapidly gaining importance in nanometer heterogeneous integrated systems. Increased power density, coupled with spatio-temporal variability of chip workload, cause lateral and vertical temperature non-uniformities (variations) in the chip structure. The assumption of an uniform temperature for a large circuit leads to inaccurate determination of key design parameters. To improve design quality, we need precise estimation of temperature at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis of the designs needs to be done at multiple levels of granularity. To further investigate the flow of chip/package thermal analysis we exploit the Intel Single Chip Cloud Computer (SCC) and propose a methodology for calibration of SCC on-die temperature sensors. We also develop an infrastructure for online monitoring of SCC temperature sensor readings and SCC power consumption. Having the thermal simulation tool in hand, we propose MiMAPT, an approach for analyzing delay, power and temperature in digital integrated circuits. MiMAPT integrates seamlessly into industrial Front-end and Back-end chip design flows. It accounts for temperature non-uniformities and self-heating while performing analysis. Furthermore, we extend the temperature variation aware analysis of designs to 3D MPSoCs with Wide-I/O DRAM. We improve the DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting the per-DRAM-bank refresh period accordingly. We develop an advanced virtual platform which models the performance, power, and thermal behavior of a 3D-integrated MPSoC with Wide-I/O DRAMs in detail. Moving towards real-world multi-core heterogeneous SoC designs, a reconfigurable heterogeneous platform (ZYNQ) is exploited to further study the performance and energy efficiency of various CPU-accelerator data sharing methods in heterogeneous hardware architectures. A complete hardware accelerator featuring clusters of OpenRISC CPUs, with dynamic address remapping capability is built and verified on a real hardware.

Despite the several issues faced in the past, the evolutionary trend of silicon has kept its constant pace. Today an ever increasing number of cores is integrated onto the same die. Unfortunately, the extraordinary performance achievable by the many-core paradigm is limited by several factors. Memory bandwidth limitation, combined with inefficient synchronization mechanisms, can severely overcome the potential computation capabilities. Moreover, the huge HW/SW design space requires accurate and flexible tools to perform architectural explorations and validation of design choices. In this thesis we focus on the aforementioned aspects: a flexible and accurate Virtual Platform has been developed, targeting a reference many-core architecture. Such tool has been used to perform architectural explorations, focusing on instruction caching architecture and hybrid HW/SW synchronization mechanism. Beside architectural implications, another issue of embedded systems is considered: energy efficiency. Near Threshold Computing is a key research area in the Ultra-Low-Power domain, as it promises a tenfold improvement in energy efficiency compared to super-threshold operation and it mitigates thermal bottlenecks. The physical implications of modern deep sub-micron technology are severely limiting performance and reliability of modern designs. Reliability becomes a major obstacle when operating in NTC, especially memory operation becomes unreliable and can compromise system correctness. In the present work a novel hybrid memory architecture is devised to overcome reliability issues and at the same time improve energy efficiency by means of aggressive voltage scaling when allowed by workload requirements. Variability is another great drawback of near-threshold operation. The greatly increased sensitivity to threshold voltage variations in today a major concern for electronic devices. We introduce a variation-tolerant extension of the baseline many-core architecture. By means of micro-architectural knobs and a lightweight runtime control unit, the baseline architecture becomes dynamically tolerant to variations.

This thesis deals with heterogeneous architectures in standard workstations. Heterogeneous architectures represent an appealing alternative to traditional supercomputers because they are based on commodity components fabricated in large quantities. Hence their price-performance ratio is unparalleled in the world of high performance computing (HPC). In particular, different aspects related to the performance and consumption of heterogeneous architectures have been explored. The thesis initially focuses on an efficient implementation of a parallel application, where the execution time is dominated by an high number of floating point instructions. Then the thesis touches the central problem of efficient management of power peaks in heterogeneous computing systems. Finally it discusses a memory-bounded problem, where the execution time is dominated by the memory latency. Specifically, the following main contributions have been carried out: A novel framework for the design and analysis of solar field for Central Receiver Systems (CRS) has been developed. The implementation based on desktop workstation equipped with multiple Graphics Processing Units (GPUs) is motivated by the need to have an accurate and fast simulation environment for studying mirror imperfection and non-planar geometries. Secondly, a power-aware scheduling algorithm on heterogeneous CPU-GPU architectures, based on an efficient distribution of the computing workload to the resources, has been realized. The scheduler manages the resources of several computing nodes with a view to reducing the peak power. The two main contributions of this work follow: the approach reduces the supply cost due to high peak power whilst having negligible impact on the parallelism of computational nodes. from another point of view the developed model allows designer to increase the number of cores without increasing the capacity of the power supply unit. Finally, an implementation for efficient graph exploration on reconfigurable architectures is presented. The purpose is to accelerate graph exploration, reducing the number of random memory accesses.

Condenser MEMS microphones are becoming a promising technology to substitute the current standard microphones, and modelling such systems has become very important for designing a condenser microphone fulfilling the given constrains. In this dissertation a deep analysis of capacitive MEMS microphone has been presented coming up with a complete model which is able to fit the experimental data of the microphone sensitivity. Furthermore, a simple noise model, able to fit the experimental data, has been developed considering the well-know Brownian noise and the more subtle 1/f component, usually neglected. With such models, it is possible to have a reliable estimation of the microphone SNR. Many characterizations have been performed on the produced samples and different problems of the manufacturing process have been highlighted, gaining a deeper understanding on the structure of the microphone and on the production process. Finally, to reply to the more and more demanding constraints, two applications of control law have been applied: a force feedback and a controller to tune the resonant frequency of the microphone. This last application shows how a controller can make the system more flexible and reduce the problem of some defects on the production. The force feedback is a technique already used in MEMS systems, such as gyroscopes and accelerometers, where it has shown to be able to improve the performance of the systems. In the presented configuration, a force feedback has been implemented in a digital readout interface, realizing the so-called electromechanical sigma delta converter. Its stability has been evaluated and the improvements have been verified experimentally: due to the extra filtering action of the embedded MEMS system inside the converter loop, the A-weighted in-band noise has been reduced from -63dBA to -73dBA.

A low-cost THz sensor, with a broadband high responsivity, low noise equivalent power, and capable of working at room temperature is still a challenge. Moreover, sensor integration with signal processing electronics is required in order to realize compact systems to be used in commercial imaging applications. In this thesis, CMOS FET-based THz detectors and with integrated noise-efficient readout circuits are presented as a solution. In an attempt to improve the THz focal plane arrays state of the art, the use of an imager architecture is proposed, where each sensing element of an array can be addressed individually. This architecture provides better system performance in terms of sensitivity, resolution or speed. A first chip was fabricated in the LFoundry 0.15-µm standard CMOS technology containing a 16 x 16 staring imaging array for terahertz detection in the range of 0.8 THz to 1.5 THz. Each pixel is composed of an antenna, a FET detector, and its readout electronics (a current integrator) so as the whole matrix can be integrated simultaneously. The current integrator employs an amplifier with two offset compensation techniques (chopper and current injection) and an output saturation control by adding and subtracting voltages. A second chip composed of 15 test structures was fabricated in the STMicrolectronics 0.13 µm standard CMOS technology for terahertz detection at 600 GHz, 850 GHz and 1.5 THz. This chip contains different FET detectors (transistor and antenna) and switched-capacitor readout circuits that provide both signal amplification and filtering, improving the system SNR after each operation cycle. A comparative study of their performance is done as a first step towards a future array implementation (THz camera). For both chips, electrical and terahertz characterization results of the designed structures are presented and discussed.

In this thesis we present a novel BJT (Bipolar Junction Transistor) detector that was developed and optimized for alpha particle and radon detection and monitoring. Using functional tests, we have shown that BJT detector operated with floating base can efficiently be used for the purpose of alpha-particle and, consequently, radon gas detection. Basing on these results, we have designed and fabricated a new batch of optimized BJT detectors. The results of electrical and functional characterization of newly fabricated detectors were presented in this work. Fabricated detectors observed high gain, low leakage currents and good detection properties. In parallel to the development of the detector, we successfully designed and implemented FPGA-based readout electronics ALPHADET. Design of the board and results of electrical tests of the board along with extensive data acquired by BJT detectors coupled to the board are presented in the thesis as well. The results of radon tests acquired using BJT detector confirmed that the detector can be successfully used in systems for radon monitoring.

Custom CMOS vision sensors could offer large opportunities for ultra-low power applications, introducing novel visual computation paradigms, aimed at closing the large gap between vision technology and energy-autonomous sensory systems. Energy-aware vision could offer new opportunities to all those applications, such as security, safety, environmental monitoring and many others, where communication infrastructures and power supply are not available or too expensive to be provided. This thesis aims at demonstrating this concept, exploiting the potential of an energy-aware vision sensor, developed at FBK, that extracts the spatial contrast and delivers compressed data. As a case study, a custom stereo-vision algorithm has been developed, taking advantage of the sensor characteristics, targeted to a lower complexity and reduced memory with respect to a standard stereo-vision processing. Under specific conditions, the proposed approach has proven to be very promising, although much work has still to be done both at sensor and at processing levels.The last part of this thesis is focused on the improvement of the custom sensor. A novel vision sensor architecture has been developed, which is based on a proprietary algorithm, developed by a partner of FBK and targeted to surveillance applications. The algorithm is based on adaptive temporal contrast extraction and is very suitable to be implemented at chip level. Although the output of the algorithm has strong similarities with the spatial contrast vision sensor, it relies on temporal contrast rather than spatial one, which is much more robust for event detection applications. A first prototype of ultra-low power adaptive temporal contrast vision sensor has been developed and tested.

In the last several years, both scientific and industrial community have shown an increasing interest in range imaging due to its potential use in various application domains such as robotics, vehicle safety, gaming, mobile applications as well as many others. Among the diversity of techniques available for range detection, Time-of-Flight (TOF) offers advantages in terms of compact system realization, good performance and low required computational power. Recent works have shown a trend towards higher resolutions, with a consequent reduction of pixel size, higher modulation frequencies and demodulation contrast to allow a higher distance precision. In this thesis we propose a new concept of range camera exploiting linear-mode avalanche photodiodes as in-pixel demodulating detectors. Due to photocurrent gain modulation, avalanche photodiodes can combine optical sensing and light signal demodulation in a single device. The main advantage of the avalanche photodiode implementation is the possibility to operate at high frequencies due to its very wide bandwidth that, in turn, influences the precision in distance measurement. In a first stage, the concept was experimentally validated on single pixel structures. These measurement results encouraged the implementation of a time-of-flight image sensor. A 64x64 pixel array has been designed and fabricated in a 0.35um standard CMOS technology. The pixel pitch is 30um with a fill-factor of 25.7%. Demodulation contrast exceeds 85% at 25MHz modulation frequency. A 3D camera system demonstrates best precision of 1.9cm and a 3D frame rate of 200fps. Additional tests performed on single pixels have shown demodulation contrast as high as 80% measured at 200MHz modulation frequency.

To analyze embedded systems, engineers use tools that can simulate the performance of software components executed on hardware architectures. When the embedded system functionality is strongly correlated to physical quantities, as in the case of Cyber-Physical System (CPS), we need to model physical processes to determine the overall behavior of the system. Unfortunately, embedded systems simulators are not generally suitable to evaluate physical processes, and in the same way physical model simulators hardly capture the functionality of computing systems. In this work, we present a methodology to concurrently explore these aspects using the metroII design framework. The methodology provides guidelines for the implementation of these models in the design environment. To demonstrate the feasibility of the proposed approach, we applied the methodology to two case studies. A case study regards a binaural guidance system developed to be included into a smart rollator for older adults. The second case consists of an energy recovery device which gets energy from the heat dissipated by a high performance processor and power a smart sink able to provide cooling or to serve as a wireless sensing node.