This project was carried out as thesis work during the last semester of my Master studies Electronics Design at the Mid Sweden University. Firstly, it considers a robust and exible implementation of ITU-G4 in hardware based on earlier work, and secondly, it covers review of related work and investigation in the weaknesses of two published designs. More specically, it is an investigation on the robustness of the previously developed VHDL implementation ofthe ITU-G4 algorithm. This includes designing of a debug interface to track the compression process inside the FPGA. The nal result, when comparing to earlier work and other published designs, the ITU-G4 compression performs without any glitches or crashes at certain patterns. The maximum frame rate the design can run at is 60fps at a frame size of 752x480 and clockrate of 33.3MHz. The design is tested with three sets of images: easy, medium and complexwhich are all successfully compressed. This includes imperfect images of bar-codes and Q-codes without the need of morphological preprocessing when comparing to the published design that needs preprocessing for medium and complex images to remove unexpected transitions.