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New methodology for low power and less test time in VLSI testingLee, Il-Soo, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.
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Scalable solutions to specification and verification of large designs /Saxena, Nina, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 114-124). Available also in a digital version from Dissertation Abstracts.
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Design, fabrication and characterization of an integrated micro heat pipe system /Lee, Man. January 2002 (has links)
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 74-77). Also available in electronic version. Access restricted to campus users.
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Test plan generation technique for complex integrated circuitsLee, Songjun. January 2002 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
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A multi-abstraction level platform for the validation and verification of complex digital designsBoland, Jean-François. January 1900 (has links)
Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2007/08/29). Includes bibliographical references.
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A methodology for NMOS VLSI manufacturing : from design to test at the Rochester Institute of Technology /Chomicz, Thecla, F. January 1990 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1990. / Includes various tests and graphs. Includes bibliographical references (leaves 90-92).
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Adaptive techniques for analog and mixed signal integrated circuitsFayed, Ayman Adel, January 2004 (has links)
Thesis (Ph. D.)--Ohio State University, 2004. / Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
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Symbolic methods in simulation-based verificationYuan, Jun. January 2002 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
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Improving timing verification and delay testing methodologies for IC designsZeng, Jing, Abraham, Jacob A. January 2005 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2005. / Supervisor: Jacob A. Abraham. Vita. Includes bibliographical references.
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Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits /Lee, Kyung Tek, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 102-107). Available also in a digital version from Dissertation Abstracts.
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