The objective of the research is to model the reliability and breakdown mechanism of back-end dielectrics in integrated circuits and to investigate the impact of physical design characteristics on the back-end dielectric reliability. As design and process complexities continue to increase, the reliability of the back-end dielectrics becomes marginal. This is mainly because the power supply voltage is not scaled at a rate comparable to feature size, which results in exponentially increasing electric fields among interconnect lines. Therefore, it is strongly desirable to be able to predict reliability or to detect design weaknesses to reliability failure during the pre-silicon verification stage. It is desirable to enable pre-silicon verification of back-end dielectric reliability based on physical design characteristics. In this research, it is shown that dielectric reliability can be modeled as a function of the critical circuit area based on the yield models. Defect clustering is taken into account by using the negative binomial statistics. The physical design characteristics will be investigated for their impact on back-end dielectric reliability. These characteristics include such factors as layout geometry, pattern density, pattern orientation, and via placement. The physical breakdown mechanism for porous back-end dielectric films is also to be investigated using Monte Carlo simulation. It is shown that the electric field is enhanced by porosity in ultra-low-k dielectric films. The electric field enhancement caused by the porosity is shown to accelerate the charge transport.