Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Ce travail se place dans le contexte du détecteur de vertex (VXD) composé de capteurs CMOS pour l'ILC, et dans celui du télescope en faisceau du projet européen AIDA. La thèse inclut les tests en faisceau des éléments du télescope AIDA : les super-plans SALAT et les échelles double faces PLUME. Elle questionne la valeur ajoutée en terme d'alignement, des couches double faces de capteurs CMOS pour le VXD de l'ILD. Une nouvelle méthode d'alignement autonome de chacune des 3 double couches du VXD grâce aux mini-vecteurs construits sur chaque zone de recouvrement inter-échelle est proposée et a été testée avec des particules de haute impulsion. Cependant, seules les particules du bruit de fond faisceau, de plus basses impulsions, permettent l'obtention d'une statistique suffisante pour cet alignement. Ce bruit de fond a alors été étudié et une estimation des taux d'occupation des capteurs du VXD a conduit à une ré-estimation des vitesses de lecture des capteurs de chaque couche du VXD. / This work was conducted in the context of a vertex detector (VXD) composed of CMOS sensors for ILD and in the context of the beam telescope of the european project AIDA. The provides the results of beam tests for the new telescope components : the SALAT super-planes and the PLUME double sided ladders. The thesis adresses the added value in terms of alignment, of double sided layers of CMOS sensors for the VXD of ILD. A new standalone alignment method of each of the three double sided layers of VXD with the mini-vectors built on each overlapping zone between the consecutive ladders is analysed. Such alignment was validated with high momentum particles. However, only the beam background particles, with lower momentum, can provide the minimum statistic for this kind of alignment. Thus, the beam background noise was studied and the occupancy rate of the VXD sensors was studied. This led to a reassessment of the readout speed for the sensors of each layer of the VXD.

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.