This thesis proposes novel methods and comprehensive analysis for power loss calculation, DC-link current and voltage ripple estimation, and bus bar design in two-level three-phase voltage source inverters (VSIs). A novel method of MOSFET voltage rise- and fall-time estimations for the switching power loss calculation is developed. The estimation accuracy is significantly improved by the proposed method. In order to provide a reference for thermal management design, inverter power loss analysis is presented. Using the parameters obtained from the semiconductor device datasheets and inverter operating conditions, power loss calculations of three types of devices, namely IGBT, MOSFET, and diode, are discussed. The conduction power loss calculations for these three devices are straightforward; and, the switching power loss of IGBTs and diodes can be obtained from the energy losses given by datasheets. However, many MOSFET datasheets do not provide the switching energy losses directly. Therefore, to acquire MOSFET switching energy losses, switching transient times must be estimated as accurately as possible. The impacts of inverter anti-parallel diode reverse recovery on the DC-link current and voltage ripples are investigated. According to the analysis, the impact of diode reverse recovery on the voltage ripple is negligible, while the RMS value of current ripple is influenced by both diode reverse recovery and inverter switching frequency. A novel method is developed to calculate the ripple current RMS value and the estimation accuracy is significantly improved. Depending on the calculated current and voltage ripples, DC-link capacitor selection is introduced. Generally speaking, failures in the DC-link capacitors take place more frequently than the failures in other parts of the inverter system, and plenty of research has been focusing on minimizing the required DC-link capacitance. As a result, the accurate estimations of DC-link current and voltage ripples are vital in the optimization methods. In addition, with the accurate estimations, the over-design in the DC-link capacitance could be reduced. Finally, the design of a practical bus bar is presented. The DC current distribution is aff ected by the numbers and locations of the DC input tabs, while the AC current distribution is influenced by the numbers and locations of the installation holes for DC-link capacitors and semiconductor devices. Furthermore, parasitic parameters of the bus bar, especially the stray inductance and voltage spikes caused by this inductance during switching turn-o transients, are also discussed from the angle of the design rules and correlation between the parameters and bus bar geometry structure. In the end, a bus bar is designed with balanced current distribution and low stray inductance. / Thesis / Doctor of Philosophy (PhD)