This thesis is to research connection process of multi-level conductor in integration circuits (ICs) manufacture technology. For the sake of sub-micro ICs which is gazed by people in the future, device¡¦s dimension have to be scaled down unceasingly; besides, the design of conductor connection of multi-level metal is also to be adopted for ULSI technology. However, the number of metal connection layer is increasing as well as the distance between wires is shorter and shorter, which leads to the fact that the RC delay time of metal interconnection is the primary reason of limiting the speed of semiconductor device while electronic signal is delivered among metal interconnection. In order to lower delay time of signal propagation, there are two parts in the following: In the aspect of lowering resistance, we substitute copper (resistance is 1.7£g£[-cm) at present for aluminum (resistance is 2.7£g£[-cm ) in the past so as to make copper be the wire for interconnection system. Furthermore, the scaled down device not only increase the current density of the wire but also increase the severity of electromigration inside the wire. Copper atoms are so heavier than aluminum atoms that copper atoms can restrain electromigration appropriately. In the aspect of decreasing capacitance, we will develop low dielectric constant (low-k). But copper with Damascene manufacture under the conditions of external operation such as temperature and electric field give rise to the fact that Cu diffuses into low-k material so easily that copper and low-k interact, which deteriorates the characteristic of the material¡Braises the leakage current and leads to the breakdown of the dielectric material. Therefore, it must be an important topic for study that we search for the dielectric barrier material with the characteristic against copper diffusion under the demand coinciding with integration process compatibility. At present, because of the material film called silicon carbide with low dielectric constant (k=4~6) attracts a lot of people¡¦s eyes deeply, it can applied to dielectric barrier technology to replace traditional dielectric barrier silicon nitride with high dielectric constant (k~8) for the purpose of alleviating delay time of the wire system. This thesis will discuss fundamental characteristics of silicon carbide film and some problems during the integration process. For instance, the impacts on silicon carbide under the conditions of fluorine plasma and thermal treatment; furthermore, this thesis will research the electric problems from the integration of low-k dielectric barrier and copper wire as well as probes into mechanism of leakage current.

This thesis presents the modeling of tool data produced during ion implantation for the prediction of wafer sheet resistance. In this work, we will use various statistical techniques to address challenges due to the nature of equipment data: high dimensionality, colinearity, parameter interactions, and non-linearities. The emphasis will be data integrity, variable selection, and model building methods. Different variable selection and modeling techniques will be evaluated using an industrial data set. Ion implant processes are fast and depending on the monitoring frequency of the equipment, late detection of a process shift could lead to the loss of a significant amount of product. The main objective of the research presented in this thesis is to identify any ion implant parameters that can be used to formulate a virtual metrology model. The virtual metrology model would then be used for process monitoring to ensure stable processing conditions and consequent yield guarantees. / text

This thesis describes the fabrication of a set of bright, visible light-emitting silicon LEDs. These devices were fabricated in-house at the University of Saskatchewan using a custom plasma ion implantation tool, an annealing furnace, and a physical vapour deposition system. A high-fluence (F = 4 × 1015 cm^−2) implantation of molecular hydrogen ions extracted from an RF inductively coupled plasma at an energy of 5 keV was used to create a heavily damaged region in the silicon centered approximately 40 nm below the silicon surface with a width of approximately 56 nm. A matrix of annealing (e.g. thermal processing) processes at 400 ºC and 700 ºC and different durations (30 minutes and 2 hours) as well as an aluminum gettering procedure were tested with the goal of increasing the output electroluminescence intensity. Current-voltage characterization was used to extract information about the defect-rich nanocrystalline, light-emitting layer as well as the Schottky barrier height. This enabled comparison of these new devices with previous silicon LEDs based on porous silicon and other approaches. The processes which were used to fabricate these devices are compatible with standard CMOS processing techniques and could provide one solution to the problem of optical interconnect on multi-core chips. The scientific significance of this work is the demonstration of bright, visible light emission at mean photon energies ∼1.84 eV corresponding to a photon wavelength of λ ≈ 675 nm. This is remarkable given that ordinary crystalline silicon is an indirect bandgap material with a bandgap energy of 1.1 eV, in which band-to-band radiative recombination is forbidden by momentum conservation. The devices fabricated in this thesis have light emission properties similar to previous silicon LEDs based on nanocrystalline or nanoporous silicon. They have the advantage of being easily electrically driven. The nanocrystalline region which is the source of the light emission was nucleated from the ion-implanted layer below the surface of the silicon. This makes these devices mechanically robust and insensitive to environmental conditions. The engineering significance of this work is the production of CMOS compatible light emitters. This study demonstrated increased light emission efficiency at higher annealing temperatures which is likely due to enhanced diffusion and nucleation of silicon nanocrystals in the ion-implant damaged layer.