Die Arbeit befasst sich mit der Verbesserung und Erweiterung eines bestehenden Softwareprojektes zum Streaming von JPEG-Bildern per RTP. In diesem Projekt werden JPEG-Bilder aus MJPEG-Dateien von einem Server zum Client übertragen. Um eine fehlerfreie Übertragung zu gewährleisten, soll zuvor die Eignung der Dateien für eine solche geprüft werden. Die entsprechenden Anforderungen finden sich in RFC 2435, welcher die Übertragung von JPEG-Bildern per RTP standardisiert. Zur Automatisierung der Überprüfung wurde diese in einem eigenen Programm implementiert. Weitere Verbesserungen wurden hinsichtlich der Ausführbarkeit des Projektes auf verschiedener Hardware getroffen. So wurden interne Algorithmen verbessert, um auch auf schwächerer Hardware einen flüssigen Ablauf zu ermöglichen. Außerdem wurde die Kompatibilität der RTSP-Implementierung im Projekt mit jener im VLC Media Player hergestellt. Zuletzt wurde das Softwareprojekt hinsichtlich der Verschlüsselung der Übertragung erweitert. Die Grundlage dafür legt die Anlayse von Anforderungen an die Verschlüsselung von Mediendaten. Es wurden zwei verschiedene Verfahren betrachtet und implementiert: Zum einen das weitverbreitete SRTP-Protokoll, zum anderen eine eigene JPEG-Verschlüsselung. Anschließend wurde die Komplexität der Entwicklung eines Verschlüsselungsverfahrens gezeigt, indem das selbst ent wickelte Verfahren durch einen Ersetzungsangriff gebrochen wurde. / This work deals with the improvement and extension of an existing software project for streaming JPEG images via RTP. In the project JPEG images are read in from MJPEG files and transmitted from a server to a client. To guarantee a faultless transmission the fitness of the files for transmission should be checked. The corresponding requirements can be found in RFC 2435 in which the transmission of JPEG images via RTP is standardized. An automation of this verification is realized in an own program. Further improvements are done in regard to the executability of the project on different hardware. Internal algorithms are improved to get a smooth execution even on weaker hardware. Additionally the compatibility of the implementation of RTSP in the project with that in the VLC Media Player is established. Finally the software project is extended in terms of the encryption of the transmission. The requirements of media data encryption are analyzed and used as the base for the following considerations. There are two operations which were examined and implemented: On the one hand the SRTP protocoll which is widely used. On the other hand an own JPEG encryption. Following that the complexity of developing an own encryption method is shown by breaking the developed JPEG encryption with a replacement attack.

<p>This thesis describes the design of fast JPEG processing accelerators for a DSP processor. </p><p>Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. </p><p>First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog. </p><p>Extension of the accelerator instructions was given following a custom design flow.</p>

This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog. Extension of the accelerator instructions was given following a custom design flow.

This thesis deals with the management of digital photos by metadata contained in the photos. The thesis describes the structure of the formats JFIF, TIFF, RAW and EXIF format for storing metadata into photos. In the next part of this thesis is described the design and implementation of a simple photo management application. The main functionality of the application is focused on bulk editing EXIF metadata in the photos. In the conclusion of this thesis there's a proof of results and discussion about further extension options.