Memory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced by scan cells in scan-based design. However, the bits in memory arrays cannot be replaced by scan cells, due to the area cost and the timing-critical nature of many of the paths into and out of memories. Thus, bits in a memory array can be considered non-scan storage elements. Test methods such as memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these tests aren’t sufficient to test the paths through the memory arrays. During structural (scan) test generation, memory arrays are treated as “black boxes” or memory arrays are bypassed to a known value. Black boxes decrease coverage loss while bypassing increases chip area and delay. Path delay test through memory arrays is proposed using pseudo functional test (PFT) with K Longest Paths Per Gate (KLPG). In this technique, any longest path that is captured into a non-scan cell (including a memory cell) is propagated to a scan cell. The propagation of the captured value from non-scan cell to scan cell occurs during low-speed clock cycles. In this work, we assume that only one extra coda cycle is sufficient to propagate the captured value to a scan cell. This is true if the output of the memory feeds combinational logic that in turn feeds scan cells. When we want to launch a transition from a memory output, different values are written into different address locations and the address is toggled between the locations. The ATPG writes the different values into the memory cells during the preamble cycles. In the case of launching a transition out of a non-scan cell, the cell must be written with an initial value during the preamble cycles, and the next value set on the non-scan cell input. Thus, it is possible to capture and launch transitions into and from memory and non-scan cells and thus test the path delay of the longest paths into and out of memory and non-scan cells.