The major goal of this study was to gain a better understanding of the effects that grain boundaries have on conduction in multilayer ceramic (MLC) capacitors. Electrical measurements were made so that current-voltage curves and impedance plots could be constructed. It was found that the current-voltage curves of new COG and X7R multilayer ceramic capacitors are both ohmic at low voltages and super-ohmic at intermediate voltages. Ohmic behavior prevails at high voltages for both types. Such behavior can be attributed to grain boundaries. Grain boundary resistance was clearly exhibited by X7R-type density blanks and one commercially manufactured type of X7R MLC capacitor, while the NPO density blank and two different values of Z5U multilayer ceramic capacitors, each from a different manufacturer, indicated the possibility of grain boundary resistance. All of the samples that were tested showed possible, if not probable, evidence of grain resistance. Only the Z5U-type density blank showed a resistance contribution from the bulk-electrode interfaces. A model for the grain boundary potential barrier height was developed. It was found that barrier height reduction occurs for small grain sizes due to depletion of the grain, and for increased grain curvature. Dopant effects are also responsible for barrier height reduction. These results, and the related modelling, indicate that grain boundary contributions to titanate-based ceramic resistance can vary widely from sample to sample, since there are so many material dependent variables involved. Such measurements as those described here can help clarify how grain boundaries and other factors contribute to ceramic resistance. / M.S.