Cellular arrays of processors are suitable for implementing algorithms that have a substantial amount of inherent parallelism. This thesis describes an algorithm for growing interconnection paths between processors in order to map a pattern on a fault tolerant multiprocessor array. The array uses an eight port routing switch whose hardware design and simulation is discussed in the research. The time taken to grow the paths using the proposed algorithm is evaluated with the help of timing equations derived in this thesis. Finally the effect of reducing switch hardware is investigated at both the switch level and the system level. The effect at the system level is evaluated by mapping seven different array patterns on the array and doing a probability analysis to estimate the number of switch failures required to cause array reconfiguration. It is shown that although reduction in switch hardware increases the individual switch reliability, it has a detrimental effect on the system reliability. It is also seen that the probability of array reconfiguration increases with time and pattern size. / Master of Science