This research presents an analysis of the improvement in the performance of a class of fault tolerant multistage interconnection networks. In the network discussed here, fault tolerance is achieved by providing multiple redundant paths between the source and destination. The extra paths are obtained by providing redundant links between switching elements within a stave (intra-stage links), thereby increasing the switching element complexity. The techniques used in the construction of this network, its properties, advantages, and disadvantages are discussed. While early studies focused their effort in analyzing the fault tolerant characteristics of the network and the performance in a circuit switched environment, this investigation complements the previous work by examining fie performance of a packet switched network. The reasons for the choice of the architecture that include factors like hardware complexity, cost and simplicity of control algorithm are analyzed. The study concentrates on improving the run-time performance of the fault tolerant network. by using these multiple paths not only in the presence of a fault, but also in a fault-free environment. The throughput of the packet switched network in the presence of a fault, congestion and when fault free are analyzed. A description of the investigation, assumptions and factors used for the study, a cost analysis, and the results of the simulation analyses is included. / Master of Science