With a decreasing minimum feature size in very large scale integration (VLSI) complementary metal oxide semiconductor (CMOS) technology, the number of transistors that can be integrated on a single chip is increasing rapidly. Ensuring that these extremely dense chips are almost free of defects, and at the same time, cost-effective requires planning from the initial stage of design. This research proposes a concurrent engineering-based design methodology for layout optimization. The proposed method for layout optimization is iterative, and layout changes in each design iteration are made based on the principles of physical design for testability (P-DFT). P-DFT modifies a design such that the circuit has fewer faults, difficult to detect faults are made easier to detect, and difficult to detect faults are made less likely to occur. To implement this design methodology, a mathematical model is required to evaluate alternate designs. This research proposes an evaluation measure: the cost quality model. The cost quality model extends known test quality and testability estimation measures for gate-level circuits to switch-level circuits. To provide high fidelity in testability estimation and reasonable CPU time overhead, the cost quality model uses inductive fault analysis techniques to extract a realistic circuit fault list, I_DDQ test generation techniques to generate tests for these faults, statistical models to reduce computational overhead due to test generation and fault simulation, yield simulation tools, and mathematical models to estimate test quality and costs. To demonstrate the effectiveness of this model, results are presented for CMOS layouts of benchmark circuits and modifications of these layouts. / Master of Science