Partial scan has served as an alternative solution for test generation for sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a test generation based method and aims to find the conditions that can lead to the detection of as many aborted faults as possible. The faults aborted by a sequential automatic test pattern generator (ATPG) are targeted in ETA and the requirements for the detection of the faults are used for the selection of scan flip-flops. The Extended Tracking Algorithm is realized in two different algorithms, optimal and heuristic, depending on the objectives. The optimal algorithm guarantees the minimal set of flip-flops for the detection of all of the aborted faults in a given circuit, but it has exponential worst case complexity. The heuristic algorithm, on the other hand, obtains a near optimal solution in shorter time. ETA provides a spectrum of accurate fault efficiency and/or fault coverage so that the designer can choose an affordable option. The method is simple and compatible with other scan flip-flop selection approaches. We implemented the Extended Tracking Algorithm in a program called BELLONA. Experiments have been conducted on ISCAS89 benchmark circuits with different specifications. Our experimental results show that ETA is an efficient solution for partial scan deign and only a small portion of scan flip-flops are necessary to obtain extremely high fault efficiency. / M.S.