A computer system is defined to be a system of n functional components interconnected together in a prescribed fashion to perform a variety of functions. To ensure the correctness of system output, faults in the system must be detected, and faulty component(s) subsequently identified. To continue operation with degraded performance the system reconfigures with the remaining resources. This ideal fault tolerant capability hinges on the capability of the system to detect and locate fault(s). One method is to perform a fault diagnosis procedure periodically. In the PMC (Preparata, Metze, and Chien) model, each component has the capability to test and be tested at the system level by a combination of other components in the system. Based on this model, a number of fault diagnosis algorithms have been developed. These fault diagnosis algorithms are either complicated or have inherited the diagnostic hardcore problem or both. In this thesis, an innovative approach to system level fault diagnosis is taken. A diagnosis device implemented by simple hardware is proposed that virtually eliminates the burden of complicated diagnosis algorithm and reduces the complexity of the diagnostic hardcore. This device is called a Testable Diagnosis Array, or TDA. It is constructed with very simple combinational logic cells. Its simplicity makes external testing easy. The diagnosis procedure is thus transferred to the logic of the cell and to the control structure of the TDA. In this thesis, a TDA is defined based on the PMC model. A simple algorithm is developed to construct a TDA for any given system. The TDA is characterized, with respect to the testing assignments of a system. A class of t-TDA-diagnosable systems is defined. Necessary and sufficient conditions for t-TDA-diagnosable systems are derived. A number of special classes oft-diagnosable systems are shown to be t-TDA-diagnosable. Other results and topics for future research are discussed. / Ph. D.