Current methodologies for built-in test pattern generation usually employ a predetermined linear feedback shift register (LFSR) in order to generate or decompress deterministic test patterns. As a direct consequence, the test pattern computation and the fault coverage are constrained to the preselected architecture. Work has been done to determine desirable characteristics in the LFSR to be used. Also, work has been done in the use of these predefined architectures, in order to compact the test data. In general, these methodologies take advantage of the large amount of don't care bits present in the test patterns, to accommodate the few specified bits to the output generated by the predefined LFSR. This dissertation explores the design of the LFSR as a built-in mechanism for test pattern generation in integrated circuits. The advantage of designing such devices is that the test set generation process is not constrained to a predefined LFSR mechanism, and the fault coverage is not affected. The methodologies presented in this work are based on cryptography concepts and heuristics to perform its computation. First, it is shown how these concepts can be adapted to test pattern generation. After this, methodologies are presented to generate one-dimensional and two-dimensional test sets. For the case of two-dimensional test set, the design of phase shifters is included.

University, Diss., 2004--Mannheim.

The thesis deals with the theory and design of the network traffic generator on the FPGA platform. The VHDL programming language is used for the description. The work involves getting acquainted with the development processes and design tools needed to create the overall project. It also includes familiarity with the necessary FPGA, NetCOPE and COMBO cards. Based on this information, was designed, tested and implemented packet generator project for the Combo-80G card. For implementation was used framework from NetCOPE.

The linear feedback shift-register is a widely used tool for generating cryptographic sequences. The properties of the Galois model discussed here offer many opportunities to improve the implementations that already exist. We explore the overall properties of the phases of the Galois model and conjecture a relation with modular Golomb rulers. This conjecture points to an efficient method for constructing non-linear filtering generators which fulfil Golic s design criteria in order to maximise protection against his inversion attack. We also produce a number of methods which can improve the rate of output of sequences by combining particular distinct phases of smaller elementary sequences.

In this work we study cryptanalysis one of the most current stream ciphers A5/1. The cipher is used to provide mobile communication privacy in the GSM cellular telephone standard. An essential element of the cipher A5/1 is LFSR( Linear feedback shift register) which is used in stream ciphers because it produces a sequence of bits with high periodicity, has good statistical properties and is easily analyzed using various algebraic methods. At work, we describe and implement three known-plaintext attacks on the cipher. The first two attacks are of the type Guess and Determine and the last one is correlation attack. The focus of the work is cryptanalysis by Golić, which assumes only 64 bits of plaintext. The character of implementation allows to split the work and use parallel-computing, making it possible to use the program in practice. At the end of the work we devote to correlation attack, that is considerably faster, but it assumes knowledge of the relatively large amount of plaintext.

The advancements of semiconductor processing technology have led to the ability for computing platforms to operate on large amounts of data at very high clock speeds. To fully utilize this processing power the components must have data continually available for operation upon and transport to other system components. To enable this data requirement, high speed serial links have replaced slower parallel communication protocols. Serial interfaces inherently require fewer signals for communication and thus reduce the device pin count, area and cost. A serial communication interface can also be run at a higher frequency because the clock skew between channels is no longer an issue since the data transmitted on various channels is independent. Serial data transmission also comes with a set of drawbacks when signal integrity is considered. The data must propagate through a channel that induces unwanted effects onto the signals such as intersymbol interference. These channel effects must be understood and mitigated to successfully transmit data without creating bit errors upon reception at the target component. Previously developed adaptive equalization techniques have been used to filter the effects of intersymbol interference from the transmitted data in the signal. This report explores the modeling and implementation of a system comprised of a transmitter, channel, and receiver to understand how intersymbol interference can be removed through a decision-feedback equalizer realized in hardware. The equalizer design, implementation, and measurements are the main focus of this report and are based on previous works in the areas of integrated circuit testing, channel modeling, and equalizer design. Simulation results from a system modeled in Simulink are compared against the results from a hardware model implemented with an FPGA, analog to digital converter and discrete circuit elements. In both the software and hardware models, bit errors were eliminated for certain amounts of intersymbol interference when a receiver with decision-feedback equalization was used instead of a receiver without equalization. / text

The gap between abstract, mathematics-oriented research in cryptography and the engineering approach of designing practical, network security protocols is widening. Network researchers experiment with well-known cryptographic protocols suitable for different network models. On the other hand, researchers inclined toward theory often design cryptographic schemes without considering the practical network constraints. The goal of this dissertation is to address problems in these two challenging areas: building bridges between practical network security protocols and theoretical cryptography. This dissertation presents techniques for building performance sensitive security protocols, using primitives from linear feedback register sequences (LFSR) sequences, for a variety of challenging networking applications. The significant contributions of this thesis are: 1. A common problem faced by large-scale multicast applications, like real-time news feeds, is collecting authenticated feedback from the intended recipients. We design an efficient, scalable, and fault-tolerant technique for combining multiple signed acknowledgments into a single compact one and observe that most signatures (based on the discrete logarithm problem) used in previous protocols do not result in a scalable solution to the problem. 2. We propose a technique to authenticate on-demand source routing protocols in resource-constrained wireless mobile ad-hoc networks. We develop a single-round multisignature that requires no prior cooperation among nodes to construct the multisignature and supports authentication of cached routes. 3. We propose an efficient and scalable aggregate signature, tailored for applications like building efficient certificate chains, authenticating distributed and adaptive content management systems and securing path-vector routing protocols. 4. We observe that blind signatures could form critical building blocks of privacypreserving accountability systems, where an authority needs to vouch for the legitimacy of a message but the ownership of the message should be kept secret from the authority. We propose an efficient blind signature that can serve as a protocol building block for performance sensitive, accountability systems. All special forms digital signatures—aggregate, multi-, and blind signatures—proposed in this dissertation are the first to be constructed using LFSR sequences. Our detailed cost analysis shows that for a desired level of security, the proposed signatures outperformed existing protocols in computation cost, number of communication rounds and storage overhead.

No description available.

This thesis is mainly focused on FRC (Frame Rate Control) method which can be used for LCD panels, where a new algorithm is proposed to improve the flicker problem. The proposed algorithm can be implemented by simple digital circuits with low power consumption. The proposed design can be applied in both mono- and color- STN panels. It can generate 32768 colors in a panel without any flicker and motion line problems, which can only allow 8 colors originally. The major contribution in this thesis is to add a location number to each pixel of the panel.Notably, the numbers for all the pixels can not be a regular pattern. Otherwise, the flicker problem is resolved at the expense of a serious motion line issue. The consequence is poor display quality. To resolve both the flicker and motion line problem, we propose to employ a PRSG (Pseudo Random Sequence Generator) which generates a non-regular number sequence for all the pixels. Therefore, all the ON pixels can be dispersed on the panel in all frames.

Generating functions are important tools that are used in many areas of mathematics and especially statistics. Besides analyzing the general structure of sequences and their asymptotic behavior / these functions, which can be roughly thought as the transformation of sequences into functions, are also used effciently to solve combinatorial problems. In this thesis, the effects of the transformations of generating functions on their corresponding sequences and the effects of the change in sequences on the generating functions are examined. With these knowledge, the generating functions for the resulting sequence of some combinatorial problems such as number of partitions, number of involutions, Fibonacci numbers and Catalan numbers are found. Moreover, some mathematical identities are proved by using generating functions. The sequences are the bases of especially symmetric key cryptosystems in cryptography. It is seen that by using generating functions, linear complexities and periods of sequences generated by constant coeffcient linear homogeneous recursions, which are used in linear feedback shift register (LFSR) based stream ciphers, can be calculated. Hence studying generating functions leads to have a better understanding in them. Therefore, besides combinatorial problems, such recursions are also examined and the results are used to observe the linear complexity and the period of LFSR&rsquo / s combined in different ways to generate &ldquo / better&rdquo / system of stream cipher.