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Closed set logic in categories / William James.James, William, 1968- January 1996 (has links)
Bibliography: leaves 263-266. / v, 266 leaves ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis investigates two related aspects of a dualisation program for the intuitionist logic in categories. The dualisation program has as its end the presentation of closed set logic in place of the usual open set logic found in association with toposes. The study is concerned especially with Brouwerian algebras in categories as the duals of the usual Heyting algebras. Defines the notion of a sheaf over the closed sets of a topological space. Investigates the sheaves for their algebric properties in relation to base space topologies. / Thesis (Ph.D.)--University of Adelaide, Dept. of Philosophy, 1996
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Closed set logic in categories / William James.James, William, 1968- January 1996 (has links)
Bibliography: leaves 263-266. / v, 266 leaves ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis investigates two related aspects of a dualisation program for the intuitionist logic in categories. The dualisation program has as its end the presentation of closed set logic in place of the usual open set logic found in association with toposes. The study is concerned especially with Brouwerian algebras in categories as the duals of the usual Heyting algebras. Defines the notion of a sheaf over the closed sets of a topological space. Investigates the sheaves for their algebric properties in relation to base space topologies. / Thesis (Ph.D.)--University of Adelaide, Dept. of Philosophy, 1996
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The best imperative approach to deontic discourseSuzuki, Makoto, January 2007 (has links)
Thesis (Ph. D.)--Ohio State University, 2007. / Full text release at OhioLINK's ETD Center delayed at author's request
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Hazard detection with VHDL in combinational logic circuits with fixed delays /Chu, Ming-Cheung, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 181-182). Also available via the Internet.
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Bisimulation quantifiers for modal logics /French, Timothy Noel. January 2006 (has links)
Thesis (Ph.D.)--University of Western Australia, 2006.
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Meaning, generality, and rules : language and logic in the later Wittgenstein /Loomis, Eric John, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 386-407). Available also in a digital version from Dissertation Abstracts.
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Efficient VHDL models for various PLD architectures /Giannopoulos, Vassilis. January 1995 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.
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Calculus students' knowledge of the composition of functions and the chain ruleHassani, Sarah. Dossey, John A. January 1998 (has links)
Thesis (D.A.)--Illinois State University, 1998. / Title from title page screen, viewed July 3, 2006. Dissertation Committee: John A. Dossey (chair), Roger Day, Michael Marsali, Michael Plantholt. Includes bibliographical references (leaves 196-202) and abstract. Also available in print.
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Capturing temporal aspects of bio-health ontologiesLeo, Jared January 2016 (has links)
Extending Descriptions Logics (DLs) with a temporal dimension to aid in the ability to model meaningful temporal information is an active and popular research area that has gathered a lot of attention over recent years. DLs underpin the Web Ontology Language (OWL) which offers a way to describe ontologies for the semantic web. Representing temporal information in ontologies plays an important role, specifically for those ontologies where time information is inherently embedded in the information they describe. This is very common for ontologies in the bio-health domain, for example ontologies that describe the development of anatomies of biological entities, stage based development, evolution of diseases and so on. As expressive as DLs are, given that they are fragments of First Order Logic, they are static in nature and are limited in what they can express from a temporal view point, hence the surge in temporal extensions to DLs over recent years. In this thesis we investigate the use of temporal extensions of DLs as suitable representations for the temporal information required for bio-health ontologies. We first set out to find out exactly what types of temporal information need to be modelled, before going on to evaluate current temporal extensions and representations to determine their suitability. We then go on to introduce several new temporal extensions to DLs and evaluate their suitability.
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Building transistor-level networks following the lower bound on the number of stacked switches / Construindo redes de transistores de acordo com o número mínimo de chaves em sérieSchneider, Felipe Ribeiro January 2007 (has links)
Em portas lógicas CMOS, tanto o atraso de propagação como a curva de saída estão fortemente ligados ao número de dispositivos PMOS e NMOS conectados em série nas redes de carga e descarga, respectivamente. O estilo lógico ‘standard CMOS’ é, em geral, otimizado para um dos planos, apresentando então o arranjo complementar no plano oposto. Consequentemente, o número mínimo de transistores em série não é necessariamente alcançado. Neste trabalho, apresenta-se um método para encontrar o menor número de chaves (transistores) em série necessários para se implementar portas lógicas complexas CMOS. Um novo estilo lógico CMOS, derivado de tal método, é então proposto e comparado ao estilo CMOS convencional através do uso de uma ferramenta de caracterização comercial. A caracterização elétrica de conjuntos de funções de 3 a 6 entradas foi realizada para avaliar o novo método, apresentando significativos ganhos em velocidade, sem perdas em dissipação de potência ou em área. / Both the propagation delay and the output slope in CMOS gates are strongly related to the number of stacked PMOS and NMOS devices in the pull-up and pull-down networks, respectively. The standard CMOS logic style is usually optimized targeting one logic plane, presenting then the complemented topology in the other one. As a consequence, the minimum number of stacked transistors is not necessarily achieved. In this work, a method to find the lower bound of stacked switches (transistors) in CMOS complex gates is presented. A novel CMOS logic style, derived from such method, is then proposed and compared to conventional CMOS style through a commercial cell characterizer. Electrical characterization of sets of 3- to 6-input functions was done in order to evaluate the new method. Significant gains in propagation delay were obtained without penalty in power dissipation or area.
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