As advances in very large scale integration (VLSI) technology lead to higher levels of circuit integration and new design styles and fabrication processes, traditional test generation techniques fail to adequately address the problems of how to (l) accurately represent the structure of design styles and physical faults, and (2) manage the high computational costs and memory resource requirements caused by the complexity of VLSI. This research investigates a modular, hierarchical approach to test generation for combinational complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design techniques are used in the development of a hierarchical test generation application implemented using C++. In doing this, the primary objectives were to produce a easily maintainable system, provide an extensible framework for test generation supporting the straightforward incorporation of new types of circuit primitives and faults, and retain the same level of computational efficiency that can be achieved using a procedural language such as C. Characteristics of the object-oriented hierarchical test generation application, such as expandability and run-time efficiency, are compared to those of a standard gate-level test generation program implemented using C and a procedural design approach. / Ph. D.

Thesis advisor: Matthias von Davier / The transition of major international large-scale assessments (ILSAs) from paper- to computer-based assessments has made process data increasingly available. While process data is potentially valuable for analyzing students’ test-taking behaviors, it also raises ethical concerns and involves considerable costs. This prompts the question: “Does process data add value to the analysis of ILSA data?” In response, this dissertation explores the utility of process data through three studies. Study 1 proposes a multiple-group hierarchical speed-accuracy-revisits model to examine the gender differences in mathematics ability, response speed, revisit propensity, and the relationships among them. The model’s flexibility allows it to be applied in diverse contexts to investigate group differences in test-taking behaviors and achievement beyond gender. Study 2 addresses the overparameterization challenge in ILSA scaling by proposing a new approach: adding process variables to the usual contextual variables and replacing principal component analysis with variable selection for latent regression modeling. The findings show that process variables consistently improved measurement precision; using Lasso, random forests, and ultimately gradient boosting for variable selection achieved or surpassed the measurement precision of the conventional approach but with considerably fewer covariates. Integrating variable selection and process data yielded the highest measurement precision while achieving parsimony, demonstrating the effectiveness of the proposed method. Study 3 investigates students’ test-taking behaviors in the context of girls consistently outperforming boys on average across countries and assessments. Three types of test-taking behaviors were identified through latent class analysis: “Rapid”, “Challenged”, and “Engaged”. Using Bolck-Croon-Hagenaars and three-step methods reveals that girls in the “Rapid” class outperformed boys on average in all countries, while there were no significant gender differences in the “Engaged” class in three of the four countries. The gender gap in reading achievement may diminish to a mild to moderate extent if boys were to behave like girls, highlighting the importance of addressing disengagement issues in ILSAs. Collectively, these three papers advance the use of process data and demonstrate its value for analyzing and reporting results of ILSA data. / Thesis (PhD) — Boston College, 2024. / Submitted to: Boston College. Lynch School of Education. / Discipline: Education.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24263号 / 情博第807号 / 新制||情||136(附属図書館) / 京都大学大学院情報学研究科数理工学専攻 / (主査)准教授 加嶋 健司, 教授 太田 快人, 教授 山下 信雄 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Procedures for the modeling and simulation of faults in LSI devices at functional level are developed. Generalized functional level fault classes are defined for digital LSI devices such as microprocessor and peripheral chips. General procedures to inject functional level faults in the LSI chip models are illustrated with the help of various examples. Next, techniques of automating the simulation of the faulty systems are discussed. Finally, simulation of faults at the functional level is compared with the gate level simulation in case of INTEL 8212 (8 bit I/O) chip. / Master of Science

An interactive color graphics layout editor for VLSI has been implemented on the IBM PC. The software, PC-ICICLE, is written in Microsoft PASCAL and the 8086/88 Assembly Language under the DOS 2.0 environment. The basic hardware requirement is the standard configuration of the IBM PC with 256K bytes, and color graphics monitor and adapter. Without the need for any special hardware, PC-ICICLE makes layout editors more readily available to VLSI chip designers. PC-ICICLE has also been executed on the IBM PC-XT, IBM PC-AT, and Zenith's IBM compatible PC without any modifications. / Master of Science

Traditional test generation techniques for digital circuits have been rendered inadequate by the increasing levels of integration achieved by VLSI technology. This thesis presents a test generation algorithm, the E-algorithm, that generates tests for circuits described using the VHDL Hardware Description Language. A fault model has been developed that addresses data path faults, faults in control structures, and faults in functional operators. The E-algorithm is able to generate tests for all modeled fault types, and handles a wide variety of circuit types, including sequential circuits. The algorithm has been implemented; preliminary results are given. / Master of Science

In this thesis, new methods to handle reconvergent fanout and feed-back during behavioral level test generation are proposed. These methods have been implemented - into a previously developed automatic test generator. The improved test generator was tested on five behavioral circuit models. For circuits with the reconvergent fanout situation, the improved test generator can generate tests completely automatically. For circuits with feed-back, user assistance in a circuit initialization step is required. Some suggestions for future development for the test generator are discussed. Examples on how to use the improved test generator are presented. / Master of Science

Delay fault testing of high speed VLSI circuits is becoming increasingly important. This thesis presents an Automatic Test Pattern Generator (ATPG), called TENOR, for transition faults. Transition faults are a special case of gate delay faults. Test generation is based on the FAN algorithm. The approach taken in this thesis is to map a transition fault into two stuck-at faults, and then generate test patterns for the stuck-at faults. A fault simulator, based on parallel pattern single fault propagation, was also developed. The problem of generating both non-robust and robust tests has been addressed. Experimental results indicate that TENOR is one of the fastest ATPGs among similar previous works, with comparable fault coverage. Experiments were also done to determine the effectiveness of stuck-at test sets and random test patterns in detecting transition faults. / Master of Science

Large scale optimization problems are tractable only if they are somehow decomposed. Hierarchical decompositions are inappropriate for some types of problems and do not parallelize well. Sobieszczanski-Sobieski has proposed a nonhierarchical decomposition strategy for nonlinear constrained optimization that is naturally parallel. Despite some successes on engineering problems, the algorithm as originally proposed fails on simple two dimensional quadratic programs. Here, the algorithm is carefully analyzed by testing it on simple quadratic programs, thereby recognizing the problems with the algorithm. Different modifications are made to improve its robustness and the best version is tested on a larger dimensional example. Some of the changes made are very fundamental, affecting the updating of the various tuning parameters present in the original algorithm. The algorithm involves solving a given problem by dividing it into subproblems and a final coordination phase. The results indicate good success with small problems. On testing it with a larger dimensional example, it was discovered that there is a basic flaw in the coordination phase which needs to be rectified. / Master of Science

An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name are provided in an interactive manner. In order to give full freedom to the user to choose the scope of checking, three options, "Flattening", "Unflattening" and "User-defined window" are implemented in creating the database to be checked. The "User-defined window" option allows hierarchical design rule checking on a design which contains global rectangles. Using these three options, very efficient hierarchical checking can be performed. / Master of Science / incomplete_metadata