Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².

Compact heat exchangers such as porous foam coldplates have great potential as a high heat flux cooling solution for electronics due to their large surface area to volume ratio and tortuous coolant path. The focus of this work was the development of unit cell modeling techniques for predicting the performance of coldplates with porous foam in the coolant path. Multiple computational fluid dynamics (CFD) models which predict porous foam coldplate pressure drop and heat transfer performance were constructed and compared to gain insight into how to best translate the foam microstructure into unit cell model geometry. Unit cell modeling in this study was realized by applying periodic boundary conditions to the coolant entrance and exit faces of a representative unit cell. A parametric study was also undertaken which evaluated dissimilar geometry translation recommendations from the literature. The use of an effective thermal conductivity for a representative orthogonal lattice of rectangular ligaments was compared to a porosity-matching technique of a similar lattice. Model accuracy was evaluated using experimental test data collected from a porous copper foam coldplate using deionized water as coolant. The compact heat exchanger testing facility which was designed and constructed for this investigation was shown to be capable of performing tests with coolant flow rates up to 300 mL/min and heat fluxes up to 290 W/cm2. The greatest technical challenge of the testing facility design proved to be the method of applying the heat flux across a 1 cm2 contact area. Based on the computational modeling results and experimental test data, porous foam modeling recommendations and porous foam coldplate design suggestions were generated.

A stacked microchannel heat sink was developed to provide efficient cooling for microelectronics devices at a relatively low pressure drop while maintaining chip temperature uniformity. Microfabrication techniques were employed to fabricate the stacked microchannel structure, and experiments were conducted to study its thermal performance. A total thermal resistance of less than 0.1 K/W was demonstrated for both counter flow and parallel flow configurations. The effects of flow direction and interlayer flow rate ratio were investigated. It was found that for the low flow rate range the parallel flow arrangement results in a better overall thermal performance than the counter flow arrangement; whereas, for the large flow rate range, the total thermal resistances for both the counter flow and parallel flow configurations are indistinguishable. On the other hand, the counter flow arrangement provides better temperature uniformity for the entire flow rate range tested. The effects of localized heating on the overall thermal performance were examined by selectively applying electrical power to the heaters. Numerical simulations were conducted to study the conjugate heat transfer inside the stacked microchannels. Negative heat flux conditions were found near the outlets of the microchannels for the counter flow arrangement. This is particularly evident for small flow rates. The numerical results clearly explain why the total thermal resistance for counter flow arrangement is larger than that for the parallel flow at low flow rates. In addition, laminar flow inside the microchannels were characterized using Micro-PIV techniques. Microchannels of different width were fabricated in silicon, the smallest channel measuring 34 mm in width. Measurements were conducted at various channel depths. Measured velocity profiles at these depths were found to be in reasonable agreement with laminar flow theory. Micro-PIV measurement found that the maximum velocity is shifted significantly towards the top of the microchannels due to the sidewall slope, a common issue faced with DRIE etching. Numerical simulations were conducted to investigate the effects of the sidewall slope on the flow and heat transfer. The results show that the effects of large sidewall slope on heat transfer are significant; whereas, the effects on pressure drop are not as pronounced.