Ho Chi Kit. / Thesis submitted in: September 2005. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 66-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.9 / Chapter 1.1 --- Aims and Contribution --- p.9 / Chapter 1.2 --- Dissertation Overview --- p.10 / Chapter 2 --- Literature Review --- p.11 / Chapter 2.1 --- ATPG-based Alternative Wiring --- p.11 / Chapter 2.1.1 --- Post-Layout Logic Restructuring for Performance Optimization --- p.11 / Chapter 2.1.2 --- Timing Optimization by an Improved Redundancy Addition and Removal Technique --- p.12 / Chapter 2.2 --- Logic Synthesis --- p.13 / Chapter 2.2.1 --- Local Logic Substitution Algorithm for Post-Layout Re-synthesis --- p.13 / Chapter 2.2.2 --- SIS: A System for Sequential Circuit Synthesis --- p.13 / Chapter 2.3 --- Fanout Optimization --- p.14 / Chapter 2.3.1 --- Efficient Global Fanout Optimization Algorithms --- p.14 / Chapter 2.3.2 --- Fanout Optimization under a Submicron Transistor-Level Delay Model --- p.15 / Chapter 2.4 --- Genetic Algorithm --- p.15 / Chapter 2.4.1 --- Scalability and Efficiency of Genetic Algorithms for Geometrical Applications --- p.15 / Chapter 2.4.2 --- "The Gambler's Ruin Problem, Genetic Algorithms, and the Sizing of Populations" --- p.16 / Chapter 3 --- Background --- p.18 / Chapter 3.1 --- Redundancy Addition and Removal --- p.18 / Chapter 3.2 --- REWIRE --- p.19 / Chapter 4 --- Standard Cell Logic Synthesis --- p.20 / Chapter 4.1 --- Introduction --- p.20 / Chapter 4.2 --- Objective --- p.22 / Chapter 4.3 --- Use Standard Patterns for Logic Synthesis --- p.22 / Chapter 4.4 --- Optimization --- p.25 / Chapter 4.5 --- Proposed Scheme --- p.26 / Chapter 4.6 --- Criteria for Selection of Wire --- p.28 / Chapter 4.7 --- Experimental Results --- p.30 / Chapter 4.8 --- Conclusion --- p.34 / Chapter 5 --- Theory on GBAW --- p.35 / Chapter 5.1 --- Introduction --- p.35 / Chapter 5.2 --- Notations and Definitions --- p.36 / Chapter 5.3 --- Minimality and Duality --- p.37 / Chapter 5.4 --- Topological Property of GBAW patterns --- p.41 / Chapter 5.5 --- Experimental Results --- p.47 / Chapter 5.6 --- Conclusion --- p.51 / Chapter 6 --- Multi-way GBAW Partitioning Scheme --- p.52 / Chapter 6.1 --- Introduction --- p.52 / Chapter 6.2 --- Algorithm of GBAW Partitioning Scheme --- p.55 / Chapter 6.3 --- Experimental Results --- p.56 / Chapter 6.4 --- Conclusion --- p.63 / Chapter 7 --- Conclusion --- p.64 / Bibliography --- p.66

Lau, Wai Shing. / Thesis submitted in: November 2006. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 85-94). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Field Programmable Gate Arrays --- p.2 / Chapter 1.2 --- FPGA technology mapping problem --- p.3 / Chapter 1.3 --- Motivations --- p.5 / Chapter 1.4 --- Contributions --- p.6 / Chapter 1.5 --- Thesis Organization --- p.9 / Chapter 2 --- Background Study --- p.11 / Chapter 2.1 --- Deterministic approach to technology mapping problem --- p.11 / Chapter 2.1.1 --- FlowMap --- p.12 / Chapter 2.1.2 --- DAOMap --- p.14 / Chapter 2.2 --- Stochastic approach --- p.15 / Chapter 2.2.1 --- Bio-Inspired Methods for Multi-Level Combinational Logic Circuit Design --- p.15 / Chapter 2.2.2 --- A Survey of Combinational Logic Circuit Representations in stochastic algorithms --- p.17 / Chapter 2.3 --- Genetic Parallel Programming --- p.20 / Chapter 2.3.1 --- Accelerating Phenomenon --- p.22 / Chapter 2.4 --- Chapter Summary --- p.23 / Chapter 3 --- A GPP based Logic Circuit Synthesizer --- p.24 / Chapter 3.1 --- Overall system architecture --- p.25 / Chapter 3.2 --- Multi-Logic-Unit Processor --- p.26 / Chapter 3.3 --- The Genotype of a MLP program --- p.28 / Chapter 3.4 --- The Phenotype of a MLP program --- p.31 / Chapter 3.5 --- The Evolution Engine --- p.33 / Chapter 3.5.1 --- The Dual-Phase Approach --- p.33 / Chapter 3.5.2 --- Genetic operators --- p.35 / Chapter 3.6 --- Chapter Summary --- p.38 / Chapter 4 --- MLP in hardware --- p.39 / Chapter 4.1 --- Motivation --- p.39 / Chapter 4.2 --- Hardware Design and Implementation --- p.40 / Chapter 4.3 --- Experimental Settings --- p.43 / Chapter 4.4 --- Experimental Results and Evaluations --- p.46 / Chapter 4.5 --- Chapter Summary --- p.50 / Chapter 5 --- Feasibility Study of Multi MLPs --- p.51 / Chapter 5.1 --- Motivation --- p.52 / Chapter 5.2 --- Overall Architecture --- p.53 / Chapter 5.3 --- Experimental settings --- p.55 / Chapter 5.4 --- Experimental results and evaluations --- p.59 / Chapter 5.5 --- Chapter Summary --- p.59 / Chapter 6 --- A Hybridized GPPLCS --- p.61 / Chapter 6.1 --- Motivation --- p.62 / Chapter 6.2 --- Overall system architecture --- p.62 / Chapter 6.3 --- Experimental settings --- p.64 / Chapter 6.4 --- Experimental results and evaluations --- p.66 / Chapter 6.5 --- Chapter Summary --- p.70 / Chapter 7 --- A Memetic GPPLCS --- p.71 / Chapter 7.1 --- Motivation --- p.72 / Chapter 7.2 --- Overall system architecture --- p.72 / Chapter 7.3 --- Experimental settings --- p.76 / Chapter 7.4 --- Experimental results and evaluations --- p.77 / Chapter 7.5 --- Chapter Summary --- p.80 / Chapter 8 --- Conclusion --- p.82 / Chapter 8.1 --- Future work --- p.83 / Bibliography --- p.85

Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata (QCA) is a new nanotechnology that claims to offer the potential of manufacturing even denser integrated circuits, which can operate at high frequencies and low power consumption. In QCA technology, the signal propagation occurs as a result of electrostatic interaction among the electrons as opposed to flow to the electrons in a wire. The basic building block of QCA technology is a QCA cell which encodes binary information with the relative position of electrons in it. A QCA cell can be used either as a wire or as logic. In QCA, the directionality of the signal flow is controlled by phase-shifted electric field generated on a separate layer than QCA cell layer. This process is called clocking of QCA circuits. The logic realization using regular structures such as PLAs have played a significant role in the semiconductor field due to their manufacturability, behavioral predictability and the ease of logic mapping. Along with these benefits, regular structures in QCA's would allow for uniform QCA clocking structure. The clocking structure is important because the pioneers of QCA technology propose it to be fabricated in CMOS technology. This thesis presents a detailed design implementation and a comparative analysis of logic realization using regular structures, namely Shannon-Lattices and PLAs for QCAs. A software tool was developed as a part of this research, which automatically generates complete QCA-Shannon-Lattice and QCA-PLA layouts for single-output Boolean functions based on an input macro-cell library. The equations for latency and throughput for the new QCA-PLA and QCA-Shannon-Lattice design implementations were also formulated. The correctness of the equations was verified by performing simulations of the tool-generate layouts with QCADesigner. A brief design trade-off analysis between the tool-generated regular structure implementation and the unstructured custom layout in QCA is presented for the full-adder circuit.

Finding an optimal solution for the logic circuit design problem is challenging and time-consuming especially for complex logic circuits. As the number of logic gates increases the task of designing optimal logic circuits extends beyond human capability. A number of evolutionary algorithms have been invented to tackle a range of optimisation problems, including logic circuit design. This dissertation explores two of these evolutionary algorithms i.e. Gene Expression Programming (GEP) and Multi Expression Programming (MEP) with the aim of integrating their strengths into a new Genetic Programming (GP) algorithm. GEP was invented by Candida Ferreira in 1999 and published in 2001 [8]. The GEP algorithm inherits the advantages of the Genetic Algorithm (GA) and GP, and it uses a simple encoding method to solve complex problems [6, 32]. While GEP emerged as powerful due to its simplicity in implementation and exibility in genetic operations, it is not without weaknesses. Some of these inherent weaknesses are discussed in [1, 6, 21]. Like GEP, MEP is a GP-variant that uses linear chromosomes of xed length [23]. A unique feature of MEP is its ability to store multiple solutions of a problem in a single chromosome. MEP also has an ability to implement code-reuse which is achieved through its representation which allow multiple references to a single sub-structure. This dissertation proposes a new GP algorithm, Improved Gene Expression Programming (IGEP) which im- proves the performance of the traditional GEP by combining the code-reuse capability and simplicity of gene encoding method from MEP and GEP, respectively. The results obtained using the IGEP and the traditional GEP show that the two algorithms are comparable in terms of the success rate when applied on simple problems such as basic logic functions. However, for complex problems such as one-bit Full Adder (FA) and AND-OR Arithmetic Logic Unit (ALU) the IGEP performs better than the traditional GEP due to the code-reuse in IGEP / Mathematical Sciences / M. Sc. (Applied Mathematics)