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abstract: Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation. This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

M.Tech.

Firms targeting high-income consumers are finding their markets becoming increasingly saturated and this has caused a shift in focus to the extensive base of low-income consumers. The opportunity and wealth that is present in the low-income segment has been iterated in numerous instances, yet the challenges to compete in this market are plentiful. To better understand the low-income market and their needs, firms need to develop strong market sensing capabilities that allow them to interpret and develop insights into this market. This report seeks to better understand the adaptive and dynamic nature of these market sensing capabilities and how firms are using these to compete in low-income markets. A qualitative design was followed where 12 senior managers from 11 firms competing in the South African low-income market were interviewed. This was facilitated by a semi-structured in-depth interview method. An inductive and deductive analysis approach was used to interpret the findings against existing models, as well as to discover new themes emerging from the data. The findings included three key themes: the use of mixed method market sensing practices to adapt to the market; improving the capability through continuous sensing, responding and learning; and influencing success by creating an adaptive internal environment. Based on these findings, a framework for competing in low-income markets using market sensing capabilities was constructed. / Dissertation (MBA)--University of Pretoria, 2013. / mngibs2014 / Gordon Institute of Business Science (GIBS) / MBA / Unrestricted

This study aimed to investigate the adoption and the use of first-order retail banking product by those individuals who are classified as being low-income earners and who reside (for the purposes of employment) in urban and periurban areas. The Financial Sector Charter of 2003 stated that the improvement and consequent increase in the access to formal financial services could contribute towards sustained economic growth, development and social transformation in South Africa. The purpose of this research is to gain insight into the adoption and usage of first-order retail banking products in an effort to better understand what could be done to improve access to these services and products. A total of 140 individuals across three sectors were interviewed with regards to their adoption of, use of and perceptions of banking institutions and bank accounts in South Africa. The results, in graphic form, were analysed in order to discern similarities and / or discrepancies so that conclusions could be drawn. It was concluded that while banking institutions and bank accounts were seen in a positive light, perceptions regarding the purpose and functionality of banking institutions and bank accounts as well as the available products and their usage, came across as being the largest hindrance to first-order retail banking product adoption and usage amongst low-income individuals in the urban and peri-urban areas. / Dissertation (MBA)--University of Pretoria, 2010. / Gordon Institute of Business Science (GIBS) / unrestricted

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Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate