Low-power digital design has been a widely researched area for the past twenty years. The growing demand for mobile computing made low power an especially important quality for such systems and encouraged researchers to find new ways of reducing power dissipation. Aggressive voltage scaling was recently published as a new paradigm for reducing power dissipation in digital circuits and the use of soft-edge flip-flops is one such technique in this category. In this thesis, we propose a soft-edge flip-flop topology that is better suited to implement the soft-edge property compared to the previously published implementations. In addition, we present the effectiveness of the soft-edge flip-flop technique by applying it to a practical VLSI design implemented with the TSMC 0.18um standard cell library. Using HSIM transistor-level SPICE simulator, we show that at least 25% power reduction is achievable in the whole circuit with a negligible area overhead. / text

This work presents improvements to a multi-core performance/power simulator. The improvements which include updated power models, voltage scaling aware models, and an application specific benchmark, are done to increase the accuracy of power models under voltage and frequency scaling. Improvements to the simulator enable more accurate design space exploration for a biomedical application. The work flow used to modify the simulator is also presented so similar modifications could be used on future simulators. / Graduation date: 2012