International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / In this paper, a small-sized low-noise integrated block downconverter (LNB) used for Ku-band direct reception from broadcasting satellites (DBS) is proposed. The operating frequency of the LNB is from 11.7 to 12.2GHz. The outlook dimension is 41 X 41 X 110mm^3. Measured results show that the average gain of the LNB is 57dB, and noise figures are less than 1.7dB. It has been found that clear TV pictures have been received using the LNB for the experiment of receiving the "BS-2b" (Japanese broadcasting satellite) at Harbin region, Heilongjiang Province, P. R. China.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2016. / Optimum communication can only be achieved with a very sensitive front-end section in the receiver on a satellite because the transmitted signal from the ground station must travel hundreds of kilometres through the earth's atmosphere to a low earth orbit (LEO) satellite. This dissertation presents the design of the front end section of the receiver suitable for use in a nano-satellite. Specifically, various transistor technologies are evaluated by designing five low noise amplifiers to determine the optimum performing amplifier. The bandwidth of the front end section was controlled by designing coupled line microstrip filter. For consistency, the same design technique was followed in the design of each LNA. Simulations were performed and the results were compared to the actual measured results of the constructed amplifiers to facilitate conclusions to be made. Design specifications for the LNAs were obtained from the F'SATI Space CubeSat Programme Technical Specification document. To control the bandwidth of the front end section, various types of band-pass filters were investigated, resulting in a coupled line band-pass filter being simulated and implemented. The simulated results were compared to the measured results of the constructed filter. In the final stage of this dissertation, comparisons of each amplifier’s performance were made, resulting in the final recommendation for this project.

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 69-72). Also available on the World Wide Web.

This thesis deals with two kinds of RF CMOS low noise amplifiers (LNA). The low power LNA and the image-reject LNA. The impact of gain, noise figure, and stability on RF CMOS image-reject LNA has been studied. Through this study, the fundamental properties of image-reject LNA can be understood by a simple but physical concept. A current-reuse RF CMOS source-degenerated cascode LNA is also presented, which adopts a combination of source-degenerated NMOS inverter and Cascode topology to improve gain and noise figure, the existent and well-studied technique from the design standpoint, makes optimization of the stage easy. A modification of the proposed architecture is also presented, which adopts internal filters to achieve the image rejection without additional image-reject filters that degrade both noise figure and power consumption. It will be a good candidate for low power implementation of CMOS RF-IC. Both circuits¡¦ parameters except noise figures are simulated using TSMC 0.25 um RF CMOS component models. The noise models considered here include induced gate noise, thermal noise and shot noise [5]. The current-reuse source-degenerated NMOS inverter LNA noise figure is 0.7 dB, forward gain is 16 dB, and IIP3 is -15 dBm. The low power image-reject LNA noise figure is 0.7 dB, forward gain is 16 dB, IIP3 is -16 dBm, and image rejection is 20 dB at 1.6 GHz. Both LNAs operate at 2.4 GHz and consume about 6 mA under a 2.5 V voltage supply.

This thesis is composed of three parts. The first part is devoted to introducing the various noise sources in transistors and their equivalent noise models. Based on the equivalent noise models, the theory of noise cancellation in a low-noise amplifier is derived in detail. The second part is to perform an experiment to validate the theory of low-noise amplifier using common-gate noise cancellation technique. By adjusting the transconductance of individual transistor, the simulated and measured noise figures are compared under different noise cancellation conditions. The third part is to design a low-noise amplifier RFIC using common-source noise cancellation technique for DVB-H applications. This RFIC was implemented in a TSMC 0.18£gm process and measured to show successful noise cancellation capability in a wide frequency range.

Thesis (M.S.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 68-70). Also available on the World Wide Web.

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design.

Thesis (Ph.D.)--Victoria University (Melbourne, Vic.), 2009.

Low-noise operational amplifiers are an important tool in the life sciences. Biosensor measurements typically rely on low-noise transimpedance amplifiers to record biological signals. Two different techniques were used to leverage the advantages of low-noise circuitry for bioelectronics. A CMOS-integrated system for measuring redox-active substrates using electrochemical read-out at very low noise levels is presented. The system incorporates 112 amplifier channels capable of current sensing with noise levels below 1 fArms in a 3.5-Hz bandwidth. The amplifier is externally connected to a gold microelectrode with a radius of 15 µm. The amplifier enables measurement of redox-couples such as potassium ferrocyanide/ferricyanide with concentrations down to 10 nM at current levels of only 300 fA. The electrochemical noise that sets the limits of detection is also measured and analyzed based on redox mass transfer equation and electrochemical impedance spectroscopy. Secondly, CMOS-integrated low noise junction field-effect transistors (JFETs) were developed in a standard 0.18-µm CMOS process. These JFETs reduce input referred flicker noise power by more than a factor of 10 when compared with equally sized n-channel MOS devices by eliminating oxide interfaces in contact with the channel. We show that this improvement in device performance translates into a factor-of-10 reduction in the input-referred noise of integrated CMOS operational amplifiers when JFET devices are used at the input.

abstract: Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation. This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014