This thesis presents a biologically inspired model of learning and development. This model decomposes the lifetime of a single learning system into a number of stages, analogous to the infant, juvenile, adolescent and adult stages of development in a biological system. This model is then applied to Kohonen's SOM algorithm.In order to better understand the operation of Kohonen's SOM algorithm, a theoretical analysis of self-organisation is performed. This analysis establishes the role played by lateral connections in organisation, and the significance of the Laplacian lateral connections common to many SOM architectures.This analysis of neighbourhood interactions is then used to develop three key variations on Kohonen's SOM algorithm. Firstly, a new scheme for parameter decay, known as Butterworth Step Decay, is presented. This decay scheme provides training times comparable to the best training times possible using traditional linear decay, but precludes the need for a priori knowledge of likely training times. In addition, this decay scheme allows Kohonen's SOM to learn in a continuous manner.Secondly, a method is presented for establishing core knowledge in the fundamental representation of a SOM. This technique is known as Syllabus Presentation. This technique involves using a selected training syllabus to reinforce knowledge known to be significant. A method for developing a training syllabus, known as Percept Masking, is also presented.Thirdly, a method is presented for preventing the loss of trained representations in a continuously learning SOM. This technique, known as Arbor Pruning, involves restricting the weight update process to prevent the loss of significant representations. This technique can be used if the data domain varies within a known set of dimensions. However, it cannot be used to control forgetfulness if dimensions are added to or removed from ++ / the data domain.

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ABSTRACT SOFT DECODING OF CONVOLUTIONAL PRODUCT CODES ON AN FPGA PLATFORM Sanli, Mustafa M.Sc., Department of Electrical and Electronics Engineering Supervisor: Asst. Prof. Dr. Ali &Ouml / zg&uuml / r YILMAZ September 2005, 79 pages In today&rsquo / s world, high speed and accurate data transmission and storage is necessary in many fields of technology. The noise in the transmission channels and read-write errors occurring in the data storage devices cause data loss or slower data transmission. To solve these problems, the error rate of the received information must be minimized. Error correcting codes are used for detecting and correcting the errors. Turbo coding is an efficient error correction method which is commonly used in various communication systems. In turbo coding, some redundancy is added to the data to be transmitted. The redundant data is used to recover original data from the received data. MAP algorithm is one of the most commonly used soft decision decoding algorithms. In this thesis, hardware implementation of the MAP algorithm is studied. MAP decoding is verified on an FPGA. Virtex2Pro is the platform of choice in this study. The algorithm is written in the VHDL language. A MAP decoder is designed and its operation is verified. Using many MAP decoders concurrently, a convolutional product decoder is implemented as well. Area and speed limitations are discussed.

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.

Level sets are extensively used for the visualization of scalar fields. The Reeb graph of a scalar function tracks the evolution of the topology of its level sets. It is obtained by mapping each connected component of a level set to a point. The Reeb graph and its loop-free version called the contour tree serve as an effective user interface for selecting meaningful level sets and for designing transfer functions for volume rendering. It also finds several other applications in the field of scientific visualization. In this thesis, we focus on designing algorithms for efficiently computing the Reeb graph of scalar functions and using the Reeb graph for effective visualization of scientific data. We have developed three algorithms to compute the Reeb graph of PL functions defined over manifolds and non-manifolds in any dimension. The first algorithm efficiently tracks the connected components of the level set and has the best known theoretical bound on the running time. The second algorithm, utilizes an alternate definition of Reeb graphs using cylinder maps, is simple to implement and efficient in practice. The third algorithm aggressively employs the efficient contour tree algorithm and is efficient both theoretically, in terms of the worst case running time, and practically, in terms of performance on real-world data. This algorithm has the best performance among existing methods and computes the Reeb graph at least an order of magnitude faster than other generic algorithms. We describe a scheme for controlled simplification of the Reeb graph and two different graph layout schemes that help in the effective presentation of Reeb graphs for visual analysis of scalar fields. We also employ the Reeb graph in four different applications – surface segmentation, spatially-aware transfer function design, visualization of interval volumes, and interactive exploration of time-varying data. Finally, we introduce the notion of topological saliency that captures the relative importance of a topological feature with respect to other features in its local neighborhood. We integrate topological saliency with Reeb graph based methods and demonstrate its application to visual analysis of features.