Scaling has been pivotal in the success of the Moore's law. Using scaling techniques to improve the MOSFET comes at a risk of growing short channel effects. This publication deals with the theoretical study of impact of gate length scaling on planar bulk MOSFET. A systematical study shows that the impact of short channel effects like drain induced barrier lowering, subthreshold leakage, hot carrier generation and channel length modulation grows with gate length scaling. Thereby degrading the MOSFET performance. In addition to the numerical device simulation an analytical modelling of the device is also performed. Though the analytical model explains the device characteristic trends, it is found to be quantitative inaccurate in comparison to the numerical model especially when scaling below deep sub-micrometer regime.