AN ABSTRACT OF THE THESIS OF Zeeshan Ahmed Bashir, for the Masters of Science degree in Electrical and Computer Engineering, presented on 29th June 2015, at Southern Illinois University Carbondale TITLE: MSB FIRST ARITHMETIC CIRCUIT FOR MOTION ESTIMATION MAJOR PROFESSOR: Dr. Haibo Wang This thesis presents a novel design of arithmetic circuits that perform computation from MSB to LSB in a serial manner. In the MSB first serial computation, the result is gradually refined along the computation cycles. If the result is used to do a comparison with a threshold, such as in motion estimation applications, it is possible to draw the comparison conclusion in the middle of the computation and subsequently skip the rest of the computation. Thus the MSB-first serial computation potentially results in significant power reduction, making them attractive to low power applications. Unlike the existing MSB-first design that uses redundant number system, the proposed design is based on the widely used 2’ complementary number system, making the proposed circuits more compact and consuming less power as compared to the existing circuits that use signed digital bit numbers. The proposed arithmetic circuits have been used to implement variable block size motion estimation (VBSME) circuits, including block sizes of 4x4, 8x4, 8x8, 8x16 and 16x16 on a Xilinx Spartan 6 FPGA device. The performance of the proposed design is compared with the design based on existing MSB-first arithmetic circuit. The comparison shows the proposed design consumes significantly less power compared to the reference design.

In recent years, there has been a significant push to implement Deep Neural Networks (DNNs) on edge devices, which requires power and hardware efficient circuits to carry out the intensive matrix-vector multiplication (MVM) operations. This work presents hardware efficient MVM implementation techniques using bit-serial arithmetic and a novel MSB first computation circuit. The proposed designs take advantage of the pre-trained network weight parameters, which are already known in the design stage. Thus, the partial computation results can be pre-computed and stored into look-up tables. Then the MVM results can be computed in a bit-serial manner without using multipliers. The proposed novel circuit implementation for convolution filters and rectified linear activation function used in deep neural networks conducts computation in an MSB-first bit-serial manner. It can predict earlier if the outcomes of filter computations will be negative and subsequently terminate the remaining computations to save power. The benefits of using the proposed MVM implementations techniques are demonstrated by comparing the proposed design with conventional implementation. The proposed circuit is implemented on an FPGA. It shows significant power and performance improvements compared to the conventional designs implemented on the same FPGA.