When a robot performs a task in an unstructured dynamic environment, it has to account for many factors. It should not only keep the track of where it is and how it should move, but also ensure that the kinematic, dynamic and task specific limitations are observed. It is also important that the robot can effectively avoid collisions with static and moving obstacles. In the current thesis we present design and implementation of an algorithm capable to face all these challenges. The system combines principles of dynamic roadmaps and elastic roadmaps frameworks, both of which are the state-of-art approaches to motion planning problem. The suggested solution is presented in the context of a broad overview of the literature in motion planning domain focusing on methodology of sample-based and feedback planning in dynamic environments. The implemented algorithm is applied to a 7-degree-of-freedom manipulator and is demonstrated and analyzed through a variety of simulated test scenarios. The result is an extensible and future-oriented planning system that can plan and execute movement between a starting and target position while preserving task constraints and reacting to environment changes in real time.

The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. While classical memory tests cover the static faults, they are not sufficient to cover dynamic faults which have emerged in VDSM technologies. The purpose of this thesis is implementation of a memory BIST that targets static faults as well as dynamic faults while maintaining an acceptable test time and area overhead.At first, and as a semester project, the functional fault models (FFMs) associated with state-of-the-art SRAM technologies have been studied and state-of-the-art memory testing algorithms, targeting these FFMs have been presented.Next, and as part of this master's thesis, a combination of March LR and March AB memory testing algorithms is selected and modified to support testing word-oriented memories. Furthermore, this algorithm is extended to provide support for detecting Data-Retention Faults. This algorithm is then implemented using Verilog HDL in Register-Transfer Level of abstraction.The implemented MemBIST is then evaluated with respect to area, performance and fault coverage. A bit-oriented March LR-based MemBIST, currently in use on Atmel® AVR® micro-controllers, is used as a reference for benchmarking purposes. All target fault primitives (FPs) have been implemented using behavioral Verilog HDL and simulated with both MemBISTs.Our evaluations show that our word-oriented MemBIST can provide a 500% performance advantage (due to the word-oriented execution) for 32-bit memories and at the same time has a better fault coverage compared to the reference MemBIST. The implemented algorithm can detect all static and realistic dynamic inter-word memory faults as well as most static and realistic dynamic intra-word faults. The implemented MemBIST also maintains a very small area overhead due to sharing the required registers with existing system components.Keywords: MemBIST, Built-In Self Test, Memory Testing, March Test, Fault Model, Fault Coverage, Fault Detection