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Microcomputer-assisted site design in landscape architecture: evaluation of selected commercial softwareHahn, Howard Davis. January 1985 (has links)
Call number: LD2668 .T4 1985 H33 / Master of Landscape Architecture
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Evaluating the accuracy of line thinning algorithms after processing scanned line dataBush, Loretta J. 31 October 2009 (has links)
The development and rapid growth of computer mapping has led to many discussions concerning the accuracy of techniques used to generate these computer representations. The purpose of this study is to analyze the accuracy of thinning methods applied to scanned map data, which is only one in a series of processes used to accomplish digital conversion of conventional maps.
In preliminary tests, nine thinning methods based on the successive layer removal process are evaluated. Seven raster images are thinned using these methods. The raster results are compared based on the number of pixels deleted and on the number of retained pixels that fall either on or off the medial axis of the original matrix. The four algorithms that produce the best results are then used for final testing.
For the final tests, 25 digital lines are plotted and scanned. The raster images are thinned using the four successive layer removal methods and a line following method developed for this study. The raster output is evaluated using the preliminary testing method. The final vector output is compared to the original input based on line length, anchor line length, and fractal dimension. / Master of Science
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Selection indices for combining marker genetic data and animal model informationRomano, Eduardo 19 September 2009 (has links)
It was suggested that marker and phenotypic information be combined in order to obtain more accurate or earlier genetic evaluations. An improvement in accuracy or time of evaluation due to utilization of marker assisted selection (MAS) increases genetic progress. Fernando and Grossman (1989) suggested including marker information directly into the Animal Model, Best Linear Unbiased Prediction system, but several problems need to be solved before their approach becomes feasible. Other selection indices were suggested but either do not use all the available information or are suitable only for evaluation of the offspring of the sire from which the marker information was established.
A selection index combining marker and Animal Model information was developed to allow comparisons involving offspring, grandoffspring and great-grandoffspring of a sire. Marker information was assumed to be a least square estimate of the difference between the average effects of the two quantitative trait loci (QTL) alleles present in a sire (D<sub>p</sub>) and the standard error of this estimate (SE(D<sub>p</sub>)). Estimates may have been obtained from a daughter or granddaughter design. Comparisons among grandoffspring and great-grandoffspring also require an estimate of the recombination rate (r) between the marker and the QTL. The Animal Model information consists of predicted transmitting ability (PTA) and reliability of PTA. PTA was assumed not to include any marker information. The expected percentage of the gain in accuracy (PGA) due to the inclusion of marker information in the selection indices is affected by the degree of polymorphism at the marker locus. The polymorphism information content (PIC) of a marker locus was computed for the second and third generations and for mates genotyped or not. PGA increased with larger Dos lower SE(D<sub>p</sub>), lower r, a smaller number of own and progeny records, and larger PIC. PGA and PIC reduce over generations. Marker information in dairy cattle is likely to be used in generations beyond offspring. Then, only the use of highly polymorphic markers with a large and accurately estimated effect may be economically justified. / Master of Science
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Evaluation de l'affectation des tâches sur une architecture à mémoire distribuée pour des modèles flot de données / Efficient evaluation of mappings of dataflow applications onto distributed memory architecturesLesparre, Youen 02 March 2017 (has links)
Avec l'augmentation de l'utilisation des smartphones, des objets connectés et des véhicules automatiques, le domaine des systèmes embarqués est devenu omniprésent dans notre environnement. Ces systèmes sont souvent contraints en terme de consommation et de taille. L'utilisation des processeurs many-cores dans des systèmes embarqués permet une conception rapide tout en respectant des contraintes temps-réels et en conservant une consommation énergétique basse.Exécuter une application sur un processeur many-core requiert un dispatching des tâches appelé problème de mapping et est connu comme étant NP-complet.Les contributions de cette thèse sont divisées en trois parties :Tout d'abord, nous étendons d'importantes propriétés dataflow au modèle Phased Computation Graph.Ensuite, nous présentons un générateur de graphe dataflow capable de générer des Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs et Phased Computation Graphs vivant avec plus de 10000 tâches en moins de 30 secondes. Le générateur est comparé à SDF3 et PREESM.Enfin, la contribution majeure de cette thèse propose une nouvelle méthode d'évaluation d'un mapping en utilisant les modèles Synchonous Dataflow Graphe et Cyclo-Static Dataflow Graphe. La méthode évalue efficacement la mémoire consommée par les communications d'un dataflow mappé sur une architecture à mémoire distribuée. L'évaluation est déclinée en deux versions, la première garantit la vivacité alors que la seconde ajoute une contrainte de débit. La méthode d'évaluation est expérimentée avec des dataflow générés par Turbine et avec des applications réelles. / With the increasing use of smart-phones, connected objects or automated vehicles, embedded systems have become ubiquitous in our living environment. These systems are often highly constrained in terms of power consumption and size. They are more and more implemented with many-core processor array that allow, rapid design to meet stringent real-time constraints while operating at relatively low frequency, with reduced power consumption.Running an application on a processor array requires dispatching its tasks on the processors in order to meet capacity and performance constraints. This mapping problem is known to be NP-complete.The contributions of this thesis are threefold:First we extend important notions from the Cyclo-Static Dataflow Graph to the Phased Computation Graph model and two equivalent sufficient conditions of liveness.Second, we present a random dataflow graph generator able to generate Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs and Phased Computation Graphs. The Generator, is able to generate live dataflow of up to 10,000 tasks in less than 30 seconds. It is compared with SDF3 and PREESM.Third and most important, we propose a new method of evaluation of a mapping using the Synchonous Dataflow Graph and the Cyclo-Static Dataflow Graph models. The method evaluates efficiently the memory footprint of the communications of a dataflow graph mapped on a distributed architecture. The evaluation is declined in two versions, the first guarantees a live mapping while the second accounts for a constraint on throughput.The evaluation method is experimented on dataflow graphs from Turbine and on real-life applications.
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