Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2003. / Includes bibliographical references (leaf 109). / Nanoscale magnetic dot arrays have attracted considerable interest, both for fundamental studies of micromagnetism and for possible applications in high-density magnetic data storage. Self-assembled block copolymers provide an alternative nanolithography technique to fabricate large-area nanomagnet arrays. Block copolymer thin films that micro-phase separate into periodic domains can be used as templates to define arrays of close-packed nanostructure, using a series of etching steps. Using polystyrene-polyferrocenyldimethyl-silane (PS-PFS), large-area polymer dots, silica dots and magnetic dots with periods of 56 nm were made using a series of plasma etching steps. Magnetometry techniques are used to characterize the bulk magnetic behavior of the dot arrays of Co, NiFe and pseudo spin valve structures. These dot arrays show strong magnetostatic interaction between the dots and within the dots. The self-assembly process is simple and low cost, however, the block copolymers typically have uncontrolled defects and lack long-range order. A topographically patterned substrate is used to guide the phase-separation in a subsequently deposited block copolymer film. The lateral dimensions of the patterns in the substrates, and interfacial interactions, are key factors in the ordering mechanism. Well-ordered block copolymer structures can be achieved under proper confinement conditions. In addition, the position of the polymer microdomains and defects in the array such as dislocations can be purposefully controlled by the design of the topographical guiding features. Combining topographic confinement with block copolymer lithographic methods will enable large-area ordered functional dot arrays to be made for various applications. / by Joy Cheng. / Ph.D.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012. / Cataloged from PDF version of thesis. / Includes bibliographical references (p. 169-165). / Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures. / by Nan Yang Pacella. / Ph.D.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2011. / Cataloged from PDF version of thesis. / Includes bibliographical references (p. 55-58). / Life cycle assessment (LCA) has gained much interest in the field of product development and decision making. The resource intensiveness of conducting an LCA has slowed more widespread adoption of the methodology. Although some streamlined LCA methodology exists and are currently be applied, there can be a lot of known and unknown uncertainties in the resulting analysis. These uncertainties could sometimes render the LCA results useless for any decision making activities. Thus this thesis proposes the evaluation of probabilistic underspecification in streamlining LCA and estimating a product's life cycle impact to both reduce LCA efforts and increase certainty in the results. This thesis focuses the development and application of probabilistic underspecification in estimating the materials impact of a product. In order to account for the uncertain with the degree of underspecificity, we propose structuring of a classification system that will help associate materials specificity, uncertainty in the materials impact, and the degree of effort to retrieve that information. This will serve as the bases for probabilistic methodology to determine what part of product is important to characterize and invest effort in order to reduce uncertainty in the LCA results with less effort than traditional LCA. Mass can be a key indicator of impact. Therefore, several case studies were conducted comparing the viability of probabilistic underspecification for calculating materials impact value for these products of varied mass compositional characteristics or the degree of mass uniformity. The compositional uniformity was measured by adapting the Herfindahl index used in economics but applied to component-mass share. Despite the difference in the mass uniformity, the methodology significantly and consistently reduced the number of components that needed to be well specified, while retaining a relatively high confidence in the resulting estimates. Probabilistic underspecification shows promise in both reducing LCA efforts and increasing the significance in the material impact assessment of the case studies in this thesis. This process also allows the leveraging of uncertainty and probability to reduce the effort and may help improve the rate at which life cycle assessment may be conducted. With faster LCA, the move towards a sustainable and environmentally responsible growth economy may be sooner realized. / by Siamrut Patanavanich. / S.M.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2005. / Includes bibliographical references (p. 147-154). / Electrochemical experiments were performed to investigate the processing-property-performance relations of thin film vanadium pentoxide cathodes used in lithium batteries. Variations in microstructures were achieved via sputtering and anneal treatments, resulting in films with different morphologies, grain size distributions, and orientations. Key findings included (1) grain size distributions largely did not affect the current rate performance of the cathodes. Rather, the film orientation and the ability to undergo rapid phase transformation were more vital to improving performance; (2) interfacial resistance and ohmic polarization were also dominant at the high current rates used (> 600 [mu]A/cm²) in addition to solid diffusion; and (3) optimization of thin film batteries requires that film thickness be < 500 nm to avoid diminishing returns in power and energy densities. Kinetic parameters including the transfer coefficient ([alpha] = 0.90± 0.05) and standard rate constant (k⁰ [approx.] 2 x 10⁻⁶ cm/s) for vanadium pentoxide films were quantified using slow scan DC cyclic voltammetry and AC cyclic voltammetry. The reaction rate was found to be potentially limiting at moderate to high current rates (> 200 [mu]A/cm²). / (cont.) An analysis of the wide variation in current-rate performance for different V₂0₅ architectures (including composite, nanofiber, and thin film) shows a convergence in results when the area of active material has been factored into the metric. This convergence suggests that either the reaction rate or interfacial resistance is limiting in V₂0₅ as opposed to diffusion. / by Simon C. Mui. / Ph.D.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2006. / In title on t.p., double-underscored "x" appears as subscript. / Includes bibliographical references. / This project considers the potential of Ge - Si₁₋x̳Gex̳ - Si substrates for solar applications. The use of compositionally graded substrates to achieve heterointegration across different materials platforms such as Si, Ge and GaAs has proven successful and dual junction solar cells have been fabricated on such substrates. The potential for graded substrates in the solar market is discussed considering the current technology, market players and worldwide renewable energy policies. A cost model is also developed and analyzed in the course of writing to assess the feasibility of this commercial enterprise. The result of these analyses highlights the technical and commercial viability of graded substrates in the solar market. / by Johnathan Jian Ming Goh. / M.Eng.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 1997. / Includes bibliographical references (leaves 176-185). / by Anil Jain. / M.S.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007. / Includes bibliographical references (p. 295-303). / Multilevel copper metallization for Ultra-Large-Scale-Integrated (ULSI) circuits is a critical technology needed to meet performance requirements for advanced interconnect technologies with sub-micron dimensions. It is well known that multilevel topography resulting from pattern dependencies in various processes, especially copper Electrochemical Deposition (ECD) and Chemical-Mechanical Planarization (CMP), is a major problem in interconnects. An integrated pattern dependent chip-scale model for multilevel copper metallization is contributed to help understand and meet dishing and erosion requirements, to optimize the combined plating and polishing process to achieve minimal environmental impact, higher yield and performance, and to enable optimization of layout and dummy fill designs. First, a physics-based chip-scale copper ECD model is developed. By considering copper ion depletion effects, and surface additive adsorption and desorption, the plating model is able to predict the initial topography for subsequent CMP modeling with sufficient accuracy and computational efficiency. Second, a compatible chip-scale CMP modeling is developed. / (cont.) The CMP model integrates contact wear and density-step-height approaches, so that a consistent and coherent chip-scale model framework can be used for copper bulk polishing, copper over-polishing, and barrier layer polishing stages. A variant of this CMP model is developed which explicitly considers the pad topography properties. Finally, ECD and CMP parts are combined into an integrated model applicable to single level and multilevel metallization cases. The integrated multilevel copper metallization model is applied to the co-optimization of the plating and CMP processes. An alternative in-pattern (rather than between-pattern) dummy fill strategy is proposed. The integrated ECD/CMP model is applied to the optimization of the in-pattern fill, to achieve improved ECD uniformity and final post-CMP topography. / by Hong Cai. / Ph.D.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008. / Includes bibliographical references (p. 46-48). / We present a general outline for automating cluster expansions of configurational energetics in systems with crystallographic order and well defined space group symmetry. The method presented herein combines constrained optimization techniques of positive-definitive quadratic forms with the mathematical tool of Tikhonov regularization (kernel smoothing) for automated expansions of an arbitrary general physical property without compromising the underlying physics. Throughout the thesis we treat formation energy as the fundamental physical observable to expand on since the predominant application of cluster expansions is the extraction of robust approximations for configurational energetics in alloys and oxides. We therefore present the implementational aspects of the novel algorithmic route on a challenging material system NaxCoO2 and reconstruct the corresponding GGA ground state line with arbitrary precision in the formation energy-configuration space. The mathematical arguments and proofs, although discussed for cases with arbitrary spin assignments and multiple candidate species for single site occupancy, are eventually formulated and illustrated for binary systems. Various numerical challanges and the way they are resolved in the framework of kernel smoothing are addressed in detail as well. However, the applicability of the procedure described herein is more universal and can be tailored to probe different observables without resorting to modifications in the algorithmic implementation or the fundemantal mathematical construction. The effectiveness in recovering correct physics shall than be solely tied to the presence of superposable nature (of the physical property of interest) of local atomic configurations or lackthereof. / by Osman Burak Okan. / S.M.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2010. / This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. / Cataloged from student submitted PDF version of thesis. / Includes bibliographical references (p. 145-151). / The synthesis of Si and III-V nanowires using the vapor-liquid-solid (VLS) growth mechanism and low-cost Si substrates was investigated. The VLS mechanism allows fabrication of heterostructures which are not readily attainable using traditional thin-film metalorganic chemical vapor deposition (MOCVD). In addition to these heterostructures, the VLS mechanism allows exploration of Si substrates as platforms for advanced III-V devices, a long-standing goal of the III-V research community, because of the potential for significant cost reductions. The approach to nanowire development first began by focusing on the binary Au/Si system. This system allowed us to understand critical parameters of our process including e-beam evaporation of Au thin-films, deposition of Au-colloid particles, pregrowth cleaning procedures and CVD growth conditions and times. Once controllable and repeatable Si nanowire epitaxy on Si substrates was established, we were able to focus on development of both III-V wires on Si substrates as well as Si substrates with topographic features and silicon-on-insulator (SOI) wafers. Growth abnormalities between Au-colloid nanoparticle catalysts and Au thin-film catalysts revealed a correlation between Au coverage on the substrate surface and Si nanowire growth rate. We found an increasing growth rate with increasing concentrations of Au catalyst particles on the wafer surface. Systematic experiments relating the nanowire growth rate to the proximity of nearest-neighbor Au-particles and Au-reservoirs were carried out and the results were found to be in good agreement with a SiH4 reaction model which associates decomposition to form SiH2 with higher nanowire growth rates. III-V nanowire growth on Si substrates was investigated as a possible route to the realization of high performance compound semiconductor devices on low cost substrates. For this study, GaP and InP were chosen as starting points for III-V nanowire integration with Si. Initial studies which focused on III-V wire epitaxy found that when Au-catalyst particles were treated with the group-III precursors before growth, there was an increase in the fraction of catalyst particles yielding wire growth and in the number of wires growing vertically from the substrate. Axial nanowire heterostructures of GaP(w)/InP(w)/GaP(w) were fabricated using MOCVD on Si (111) substrates. Growth temperature was found to be critical in the formation of GaP/InP axial heterostructures with minimal simultaneous lateral 3 overgrowth of InP. Analysis of the second GaP segment on InP suggests that an increase in growth temperature while Au is in direct contact with InP results in the InP dissolving into the Au particle and disappearance of the heterostructure. Si substrates were used as a foundation to explore more complex silicon structures, such as ordered arrays and SOI architectures. Although several routes initially looked promising for ordered array development, inverted pyramid arrays on Si (100) substrates were found to be the most successful. Silicon-on-insulator substrates were also explored for VLS nanowire growth and both Si nanowire field effect transistors and GaP nanowire cantilevers were successfully demonstrated on this platform. / by Steven Tyler Boles. / Ph.D.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 1993. / Includes bibliographical references (leaves 153-158). / by Susan Patricia James. / Ph.D.