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Design Techniques to Improve Time Dependent Dielectric Breakdown Based Failure for CMOS CircuitsTarog, Emanuel S 01 January 2010 (has links) (PDF)
This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships, and reiterate on my design and see improvements and effects.
The tool chain calculates power consumption, performance, temperature, and MTTF for a 'real life' circuit. Electric VLSI, an Electronic Design Automation tool, outputs a Spice file that yields parasitic quantities and spatial dimensions. LTspice, a high performance Spice simulator, was used to calculate the voltage and current data. Finally, I created MAP to monitor the voltage, current, and dimension data and process that in conjunction with HotSpot, a thermal modeling tool, to calculate a MTTF for each MOSFET.
Analysis of the data from the software infrastructure showed that transistor sizing played a role in the MTTF. To maximize the MTTF of a transistor in a CMOS inverter, the activity of the pull-up transistor should be balanced with the transistor in the pull-down chain, ensuring the electric fields are balanced across both transistors. While it is impossible to completely balance an arbitrary CMOS circuit's activity for an arbitrary set of input signals, circuits can be intelligently skewed to help maximize the MTTF without increasing power consumption and without sacrificing circuit performance. Consequently, attaining a maximum MTTF does not come at a cost as it is possible to design a circuit with a high MTTF that performs better and uses less power than a circuit with low MTTF.
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Design and Analysis of Adaptive Fault Tolerant QoS Control Algorithms for Query Processing in Wireless Sensor NetworksSpeer, Ngoc Anh Phan 02 May 2008 (has links)
Data sensing and retrieval in WSNs have a great applicability in military, environmental, medical, home and commercial applications. In query-based WSNs, a user would issue a query with QoS requirements in terms of reliability and timeliness, and expect a correct response to be returned within the deadline. Satisfying these QoS requirements requires that fault tolerance mechanisms through redundancy be used, which may cause the energy of the system to deplete quickly. This dissertation presents the design and validation of adaptive fault tolerant QoS control algorithms with the objective to achieve the desired quality of service (QoS) requirements and maximize the system lifetime in query-based WSNs. We analyze the effect of redundancy on the mean time to failure (MTTF) of query-based cluster-structured WSNs and show that an optimal redundancy level exists such that the MTTF of the system is maximized.
We develop a hop-by-hop data delivery (HHDD) mechanism and an Adaptive Fault Tolerant Quality of Service Control (AFTQC) algorithm in which we utilize "source" and "path" redundancy with the goal to satisfy application QoS requirements while maximizing the lifetime of WSNs. To deal with network dynamics, we investigate proactive and reactive methods to dynamically collect channel and delay conditions to determine the optimal redundancy level at runtime. AFTQC can adapt to network dynamics that cause changes to the node density, residual energy, sensor failure probability, and radio range due to energy consumption, node failures, and change of node connectivity. Further, AFTQC can deal with software faults, concurrent query processing with distinct QoS requirements, and data aggregation. We compare our design with a baseline design without redundancy based on acknowledgement for data transmission and geographical routing for relaying packets to demonstrate the feasibility. We validate analytical results with extensive simulation studies. When given QoS requirements of queries in terms of reliability and timeliness, our AFTQC design allows optimal "source" and "path" redundancies to be identified and applied dynamically in response to network dynamics such that not only query QoS requirements are satisfied, as long as adequate resources are available, but also the lifetime of the system is prolonged. / Ph. D.
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Reliability Engineering Approach to Probabilistic Proliferation Resistance Analysis of the Example Sodium Fast Reactor Fuel Cycle FacilityCronholm, Lillian Marie 2011 August 1900 (has links)
International Atomic Energy Agency (IAEA) safeguards are one method of proliferation resistance which is applied at most nuclear facilities worldwide. IAEA safeguards act to prevent the diversion of nuclear materials from a facility through the deterrence of detection. However, even with IAEA safeguards present at a facility, the country where the facility is located may still attempt to proliferate nuclear material by exploiting weaknesses in the safeguards system. The IAEA's mission is to detect the diversion of nuclear materials as soon as possible and ideally before it can be weaponized. Modern IAEA safeguards utilize unattended monitoring systems (UMS) to perform nuclear material accountancy and maintain the continuity of knowledge with regards to the position of nuclear material at a facility. This research focuses on evaluating the reliability of unattended monitoring systems and integrating the probabilistic failure of these systems into the comprehensive probabilistic proliferation resistance model of a facility.
To accomplish this, this research applies reliability engineering analysis methods to probabilistic proliferation resistance modeling. This approach is demonstrated through the analysis of a safeguards design for the Example Sodium Fast Reactor Fuel Cycle Facility (ESFR FCF).
The ESFR FCF UMS were analyzed to demonstrate the analysis and design processes that an analyst or designer would go through when evaluating/designing the proliferation resistance component of a safeguards system. When comparing the mean time to failure (MTTF) for the system without redundancies versus one with redundancies, it is apparent that redundancies are necessary to achieve a design without routine failures.
A reliability engineering approach to probabilistic safeguards system analysis and design can be used to reach meaningful conclusions regarding the proliferation resistance of a UMS. The methods developed in this research provide analysts and designers alike a process to follow to evaluate the reliability of a UMS.
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Reliability Techniques for Data Communication and Storage in FPGA-Based CircuitsLi, Yubo 11 December 2012 (has links) (PDF)
This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on field-programmable gate array(FPGA)-based circuits. It analyzes and quantifies a special case in data communication, that is, the synchronization issue of signals when they are sent across clock domains in triple modular redundancy (TMR) circuits with the presence of SEUs. After demonstrating that synchronizing errors cannot be eliminated in such case, this dissertation continues to present novel synchronizer designs that can guarantee reliable synchronization of triplicated signals. Fault injection tests then show that the proposed synchronizers provide between 6 and 10 orders of magnitude longer mean time to failure (MTTF) than unmitigated synchronizers. This dissertation also studies the reliability of block random access memory (BRAM) on FPGAs. By investigating several previous reliability models for single-error correction/double-error detection (SEC/DED) memory with scrubbing, this dissertation proposes two novel MTTF models that are suitable for FPGA applications. The first one considers non-uniform write rates for probabilistic write scrubbing, and the second one combines deterministic scrubbing and probabilistic scrubbing into a single model. The proposed models reveal the impact of memory access patterns on the reliability of BRAMs. Monte Carlo simulations then demonstrate the correctness of the proposed models. At last, the memory access patterns of a type of FPGA application, digital signal processing (DSP) is studied, and mitigation mechanisms for DSP applications are discussed.
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