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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

JDiet footprint reduction for memory-constrained systems : a thesis /

Huffman, Michael J., Dekhtyar, Alexander. January 1900 (has links)
Thesis (M.S.)--California Polytechnic State University, 2009. / Title from PDF title page; viewed on June 24, 2009. "June 2009." "In partial fulfillment of the requirements for the degree [of] Master of Science in Computer Science." "Presented to the faculty of California Polytechnic State University, San Luis Obispo." Major professor: Alexander Dekhtyar, Ph.D. Includes bibliographical references (p. 160-193).
2

Improving processor efficiency by exploiting common-case behaviors of memory instructions

Subramaniam, Samantika. January 2009 (has links)
Thesis (M. S.)--Computing, Georgia Institute of Technology, 2009. / Committee Chair: Loh, Gabriel H.; Committee Member: Clark, Nathan; Committee Member: Jaleel, Aamer; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin S.; Committee Member: Prvulovic, Milos.
3

Large object space support for software distributed shared memory

Cheung, Wang-leung, Benny., 張宏亮. January 2005 (has links)
published_or_final_version / abstract / Computer Science / Doctoral / Doctor of Philosophy
4

Multipurpose short-term memory structures.

January 1995 (has links)
by Yung, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 107-110). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Cache --- p.1 / Chapter 1.1.1 --- Introduction --- p.1 / Chapter 1.1.2 --- Data Prefetching --- p.2 / Chapter 1.2 --- Register --- p.2 / Chapter 1.3 --- Problems and Challenges --- p.3 / Chapter 1.3.1 --- Overhead of registers --- p.3 / Chapter 1.3.2 --- EReg --- p.5 / Chapter 1.4 --- Organization of the Thesis --- p.6 / Chapter 2 --- Previous Studies --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Data aliasing --- p.9 / Chapter 2.3 --- Data prefetching --- p.12 / Chapter 2.3.1 --- Introduction --- p.12 / Chapter 2.3.2 --- Hardware Prefetching --- p.12 / Chapter 2.3.3 --- Prefetching with Software Support --- p.13 / Chapter 2.3.4 --- Reducing Cache Pollution --- p.14 / Chapter 3 --- BASIC and ADM Models --- p.15 / Chapter 3.1 --- Introduction of Basic Model --- p.15 / Chapter 3.2 --- Architectural and Operational Detail of Basic Model --- p.18 / Chapter 3.3 --- Discussion --- p.19 / Chapter 3.3.1 --- Implicit Storing --- p.19 / Chapter 3.3.2 --- Associative Logic --- p.22 / Chapter 3.4 --- Example for Basic Model --- p.22 / Chapter 3.5 --- Simulation Results --- p.23 / Chapter 3.6 --- Temporary Storage Problem in Basic Model --- p.29 / Chapter 3.6.1 --- Introduction --- p.29 / Chapter 3.6.2 --- Discussion on the Solutions --- p.31 / Chapter 3.7 --- Introduction of ADM Model --- p.35 / Chapter 3.8 --- Architectural and Operational Detail of ADM Model --- p.37 / Chapter 3.9 --- Discussion --- p.39 / Chapter 3.9.1 --- File Partition --- p.39 / Chapter 3.9.2 --- STORE Instruction --- p.39 / Chapter 3.10 --- Example for ADM Model --- p.40 / Chapter 3.11 --- Simulation Results --- p.40 / Chapter 3.12 --- Temporary storage Problem of ADM Model --- p.46 / Chapter 3.12.1 --- Introduction --- p.46 / Chapter 3.12.2 --- Discussion on the Solutions --- p.46 / Chapter 4 --- ADS Model and ADSM Model --- p.49 / Chapter 4.1 --- Introduction of ADS Model --- p.49 / Chapter 4.2 --- Architectural and Operational Detail of ADS Model --- p.50 / Chapter 4.3 --- Discussion --- p.52 / Chapter 4.3.1 --- Prefetching Priority --- p.52 / Chapter 4.3.2 --- Data Prefetching --- p.53 / Chapter 4.3.3 --- EReg File Splitting --- p.53 / Chapter 4.3.4 --- Compiling Procedure --- p.53 / Chapter 4.4 --- Example for ADS Model --- p.54 / Chapter 4.5 --- Simulation Results --- p.55 / Chapter 4.6 --- Discussion on the Architectural and Operational Variations for ADS Model --- p.62 / Chapter 4.6.1 --- Temporary storage Problem --- p.62 / Chapter 4.6.2 --- Operational variation for Data Prefetching --- p.63 / Chapter 4.7 --- Introduction of ADSM Model --- p.64 / Chapter 4.8 --- Architectural and Operational Detail of ADSM Model --- p.65 / Chapter 4.9 --- Discussion --- p.67 / Chapter 4.10 --- Example for ADSM Model --- p.67 / Chapter 4.11 --- Simulation Results --- p.68 / Chapter 4.12 --- Discussion on the Architectural and Operational Variations for ADSM Model --- p.71 / Chapter 4.12.1 --- Temporary storage Problem --- p.71 / Chapter 4.12.2 --- Operational variation for Data Prefetching --- p.73 / Chapter 5 --- IADSM Model and IADSMC&IDLC Model --- p.75 / Chapter 5.1 --- Introduction of IADSM Model --- p.75 / Chapter 5.2 --- Architectural and Operational Detail of IADSM Model --- p.76 / Chapter 5.3 --- Discussion --- p.79 / Chapter 5.3.1 --- Implicit Loading --- p.79 / Chapter 5.3.2 --- Compiling Procedure --- p.81 / Chapter 5.4 --- Example for IADSM Model --- p.81 / Chapter 5.5 --- Simulation Results --- p.84 / Chapter 5.6 --- Temporary Storage Problem of IADSM Model --- p.87 / Chapter 5.7 --- Introduction of IADSMC&IDLC Model..........: --- p.88 / Chapter 5.8 --- Architectural and Operational Detail of IADSMC & IDLC Model --- p.89 / Chapter 5.9 --- Discussion --- p.90 / Chapter 5.9.1 --- Additional Operations --- p.90 / Chapter 5.9.2 --- Compiling Procedure --- p.93 / Chapter 5.10 --- Example for IADSMC&IDLC Model --- p.93 / Chapter 5.11 --- Simulation Results --- p.94 / Chapter 5.12 --- Temporary Storage Problem of IADSMC&IDLC Model --- p.96 / Chapter 6 --- Compiler and Memory System Support for EReg --- p.99 / Chapter 6.1 --- Impact on Compiler --- p.99 / Chapter 6.1.1 --- Register Usage --- p.99 / Chapter 6.1.2 --- Effect of Unrolling --- p.100 / Chapter 6.1.3 --- Code Scheduling Algorithm --- p.101 / Chapter 6.2 --- Impact on Memory System --- p.102 / Chapter 6.2.1 --- Memory Bottleneck --- p.102 / Chapter 6.2.2 --- Size of EReg Files --- p.103 / Chapter 7 --- Conclusions --- p.104 / Chapter 7.1 --- Summary --- p.104 / Chapter 7.2 --- Future Research --- p.105 / Bibliography --- p.107 / Chapter A --- Source code of the Kernels --- p.111 / Chapter B --- Program Analysis --- p.126 / Chapter B.1 --- Program analysed by Basic Model --- p.126 / Chapter B.2 --- Program analysed by ADM Model --- p.133 / Chapter B.3 --- Program analysed by ADS Model --- p.140 / Chapter B.4 --- Program analysed by ADSM Model --- p.148 / Chapter B.5 --- Program analysed by IADSM Model --- p.156 / Chapter B.6 --- Program analysed by IADSMC&IDLC Model --- p.163 / Chapter C --- Cache Simulation on Prefetching of ADS model --- p.174
5

Dynamic cache-line sizes /

Van Vleet, Taylor, January 2000 (has links)
Thesis (Ph. D.)--University of Washington, 2000. / Vita. Includes bibliographical references (leaves 128-131).
6

Memory management for high-performance applications

Berger, Emery David. January 2002 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
7

Memory management for high-performance applications

Berger, Emery David 28 August 2008 (has links)
Not available / text
8

Efficient runahead execution processors

Mutlu, Onur 28 August 2008 (has links)
Not available / text
9

Enhancing memory controllers to improve DRAM power and performance

Hur, Ibrahim 28 August 2008 (has links)
Not available / text
10

Prefetch mechanisms by application memory access pattern

Agaram, Kartik Kandadai 28 August 2008 (has links)
Not available / text

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