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Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science

Developing high efficiency solar cells for lower manufacturing costs has been a key objective for photovoltaic researchers to drive down the levelized cost of energy for solar power. In this pursuit, III-V compound semiconductor based solar cells have steadily shown performance improvement at approximately 1% (absolute) increase per year, with a recent record efficiency of 46% under concentrator and 32% under AM0. However, the expensive cost has made it challenging for III-V solar cells to compete with the mainstream Silicon (Si) technology. Novel approaches to lower down the cost per watt for III-V solar cells will position them to be among the key contenders in the renewable energy sector. Integration of such high-efficiency III-V multijunction solar cells on significantly cheaper and large area Si substrate has the potential to address the future LCOE roadmaps by unifying the high-efficiency merits of III-V materials with low-cost and abundance of Si. However, the 4% lattice mismatch, thermal mismatch, polar on non-polar epitaxy makes the direct growth of GaAs on Si challenging, rendering the metamorphic cell sensitive to dislocations. The focus of this dissertation is to investigate heterogeneously integrated 1J GaAs solar cells on Si substrate using germanium (Ge) as an intermediate buffer layer that will address mitigation of defects and dislocations between GaAs active cell structure and Ge “virtual” substrate on Si. The all-epitaxial molecular beam epitaxy (MBE)-grown thin (<1 μm) hybrid GaAs/Ge “virtual” buffer approach provided 1J GaAs cell efficiency of ~10% on Si, as compared with cell structures with thick 3 μm GaAs buffers. Solar cell results were further corroborated with material analysis to provide a clear path for the reduction of performance limiting dislocations. The thin “Ge-on-Si” virtual buffer was then investigated comprehensively to understand the impact of the heterostructure on device performance. The growth, structural, morphological, and electrical transport properties of epitaxial thin-film Ge, grown by solid source MBE on Si using a two-step growth process, were investigated. High-resolution x-ray diffraction analysis demonstrated ~0.10% tensile strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt due to misfit dislocations at the Ge/Si heterointerface. Micro-Raman spectroscopic analysis further corroborated the strain-state of the Ge thin-film on Si. Cross-sectional transmission electron microscopy revealed the formation of a 90° Lomer dislocation network at the Ge/Si heterointerface, suggesting the rapid and complete relaxation of the Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphologies with surface roughness < 2 nm. Hall mobility measurements, performed within a temperature range of 77 K to 315 K, and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in the thin Ge epilayer. Additionally, capacitance- and conductance-voltage measurements were performed after fabricating the metal-oxide-semiconductor capacitors (MOS-Cs) in order to determine the effect of epilayer dislocation density on interfacial defect states (Dit), bulk trap density, and the energy distribution of Dit as a function of temperature for electronic device applications. Deep level transient spectroscopy was used to identify the location (within the Ge bandgap) of electrically active trap levels; however, no significant trap levels were detected. Finally, the extracted Dit values were benchmarked against previously reported Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained in this work were found to be comparable with other Ge MOS devices integrated on Si via alternative buffer schemes. The understanding gained from this comprehensive study of Ge-on-Si will help optimize the 1J GaAs on Si via thin Ge buffer approach, to enable a future of high efficiency low cost solar cells for terrestrial applications. / Master of Science / The global energy landscape is projected to change remarkably in the coming decades with dwindling carbon based resource reserves and escalating energy demands, necessitating large-scale adoption of cleaner alternatives, such as solar energy. However, for widespread commercial and domestic adoption of photovoltaics, the cost of solar generated electricity must become competitive with non-renewable resources such as oil or coal. Thus, achieving high efficiency solar cells and driving down cell costs are key research objectives of the photovoltaic (PV) community in order to become more self-sufficient in the energy sector. In this pursuit, III-V compound semiconductor-based solar cells have steadily outperformed all other PV technologies, but cost-prohibitive for terrestrial deployment. Si is the undisputed standard in the PV industry; thus, to make a significant step forward in the pursuit of high efficiency solar cells, a promising approach will be to integrate the superior properties of compound semiconductors with the mature technology of Si. This research systematically investigates the integration of high efficiency III-V cells with low cost, abundant Si substrates via a germanium (Ge) layer to unify the performance merits of III-V cells with the cost benefits and superior mechanical and thermal properties of Si. Concurrently, Ge has also emerged as a strong candidate to boost transistor performance at low operating voltages, primarily owing to its superior carrier mobility and ease of integration into mainstream Si process flow. This research further delves into the structural and electrical properties of the Ge on Si structure. Overall, this research demonstrates the feasibility of the use of Ge directly integrated on Si for high efficiency solar cells and low-power electronic devices.