This thesis examines the performance of the Intel 8089 integrated I/O processor through a predictive performance model for the I/O subsystem architectures available to the designer of an iAPX 86 system. The model provides system throughput estimates and is intended to be used prior to any detailed design. The derivation of the model is followed by a description of a prototype system which is used to provide actual throughput measurements. These measurements are compared with the model predictions to evaluate the model error and its utility. The model estimates are then combined with subsystem cost data to gauge the cost-effectiveness of the 8089.

Thesis (Ph. D.)--Michigan State University. Dept. of Electrical and Computer Engineering, 2006. / Title from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.