Thesis (M.S.)--Oregon State University, 2004. / Printout. Includes bibliographical references (leaves 71-72). Also available on the World Wide Web.

Thesis (Ph. D.)--University of Texas at Austin, 1998. / Vita. Includes bibliographical references (leaves 122-126). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 69-70). Also available on the World Wide Web.

No description available.

No description available.

No description available.

The proliferation of products from the consumer electronics industry (especially the communications market) has led to increasing consumer demand for cheaper, smaller form factor, efficient and low power consumption products with high computation power. This growing demand for cheaper and more efficient products has made it more desirable for Integrated Circuit (IC) manufacturers to integrate both analogue and digital circuits on the same silicon substrate in order to realise high performance mixed-signal IC's at cost effective prices. The concomitant technology advancements in the IC manufacturing process, especially in the Complementary Metal Oxide Semiconductor (CMOS) process and improvements made in the capabilities of Computer-Aided Design (CAD) tools is making greater system integration possible. However, one aspect of the process that is the bottleneck of yet further system integration and lower design lead time is test. While the digital sections of mixed-signal IC's are taking microseconds to test using well established digital structural test techniques which exploit efficient Design for Test (DFT) structures, the analogue sections are still being tested using functional test methods and consequently consume several seconds of expensive test time. The work presented in this thesis addresses the test problems associated with the analogue sections of mixed-signal IC's. Specifically, the work was aimed at developing an efficient and unified embedded mixed-signal test system capable of being adopted for both analogue circuit characterisation and production testing of mixed-signal IC's in order to reduce overall test time and cost. In this context, an Analogue Test Response Compaction Technique (ATRCT) has been developed using Delta-Sigma Modulation (AIM). This compaction technique produces a signature for an analogue macro under test, which relates to both the amplitude and frequency of the analogue output response. Fault simulation results relating to a two-stage CMOS operational amplifier and continuous-time state variable filter have shown that fault-coverage of greater than 80% is attainable when the ATRCT is employed in a production testing of linear analogue macros. Based on the ATRCT, a hardware efficient Analogue Built-In Selt-Test (ABIST) scheme is proposed. This work has also developed two characterisation techniques suitable for embedded linear analogue macros: 1) An alternative hardware efficient method of measuring the impulse response of linear analogue macros using AIM, which could be conveniently incorporated in an ABIST scheme. Simulation results of the AIM-based impulse response measurement system have shown that the accuracy of the technique is within ±0.5% of the expected impulse responses. 2) An analogue fault detection routine that uses AIM and correlation techniques to detect analogue amplitude and frequency faults within linear analogue macros. Combining the proposed AIM-based impulse response measurement technique with the proposed ABIST scheme or analogue fault detection routine will enable an efficient and unified embedded mixed-signal test system to be designed.

A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this research is the implementation and application of mixed-signal reconfigurable systems utilizing floating-gate transistors and field programmable analog/digital arrays. Basic analog circuits using floating-gate CMOS devices have been developed for this research. Floating-gate based analog circuits reduce the effects of inherent property mismatch present in analog circuits. Various circuit blocks including current mirrors, gilbert multipliers, and $G_m-C$ filters were designed and experimentally demonstrated to show reduced mismatch effects. Such floating-gate transistors and circuits are the basis for the reconfigurable systems developed in this research. To enable high-performance reconfigurable systems, sub-micron and sub-$100 nm$ CMOS process nodes were used in this research. Scaling of Floating-gate devices is a key issue at small nodes. Test structures were created to verify the programming capability for floating-gate devices at various process nodes. Experimental results show scalability of floating-gate devices along with effective charge programming ability. A floating-gate based reconfigurable mixed-signal platform using Field-Programmable Array of Analog-Digital Devices (FPAADD) has been created and experimentally verified. Further FPAADD systems augmented with a CPU based digital back-end were developed to enable greater applications for such reconfigurable systems. Experimental functionality and circuits/systems created using FPAADD based systems were demonstrated for this research work.

No description available.

No description available.