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This thesis is an exploration into the design of configurable analog block (CAB) for field programmable analog arrays (FPAAs) designed in modern complementary metal-oxide-semiconductor (CMOS) technologies. Specifically, this thesis develops a single configurable analog block (CAB) using an operational transconductance amplifier (OTA). A fully differential OTA is selected for its flexibility and the reliability of differential signals with respect to noise when compared to single-ended signals. The OTA is combined with a set of switches, controlled by a serial shift register, to allow for reconfiguration of the internal wiring, and two capacitor arrays used to fine-tune the frequency response of the circuit. Simulation results are provided for an OTA, the OTA operating in situ, and a band-pass filter, thus demonstrating the use of the CAB. A single CAB is constructed on a 0.13 µm CMOS chip. / Integrated Circuits and Systems

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A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this research is the implementation and application of mixed-signal reconfigurable systems utilizing floating-gate transistors and field programmable analog/digital arrays. Basic analog circuits using floating-gate CMOS devices have been developed for this research. Floating-gate based analog circuits reduce the effects of inherent property mismatch present in analog circuits. Various circuit blocks including current mirrors, gilbert multipliers, and $G_m-C$ filters were designed and experimentally demonstrated to show reduced mismatch effects. Such floating-gate transistors and circuits are the basis for the reconfigurable systems developed in this research. To enable high-performance reconfigurable systems, sub-micron and sub-$100 nm$ CMOS process nodes were used in this research. Scaling of Floating-gate devices is a key issue at small nodes. Test structures were created to verify the programming capability for floating-gate devices at various process nodes. Experimental results show scalability of floating-gate devices along with effective charge programming ability. A floating-gate based reconfigurable mixed-signal platform using Field-Programmable Array of Analog-Digital Devices (FPAADD) has been created and experimentally verified. Further FPAADD systems augmented with a CPU based digital back-end were developed to enable greater applications for such reconfigurable systems. Experimental functionality and circuits/systems created using FPAADD based systems were demonstrated for this research work.

Path planning and image processing are critical signal processing tasks for robots, autonomous vehicles, animated characters, etc. The ultimate goal of the path planning problem being addressed in this dissertation is how to use a reconfigurable Analog Very Large Scale Integration (AVLSI) circuit to plan a path for a Micro Aerial Vehicle (MAV) (or similar power constrained ground or sea robot) through an environment in an effort to conserve its limited battery resources. Path planning can be summarized with the following three tasks given that states, actions, an initial state, and a goal state are provided. The robot should: 1) Find a sequence of actions that take the robot from its Initial state to its Goal state. 2) Find actions that take the robot from any state to the Goal state, and 3) Decide the best action for the robot to take now in order to improve its odds of reaching the Goal. Image processing techniques can be used to visually track an object. Segmenting the object from the background is one subtask in this problem. Digital image processing can be very computationally expensive in terms of memory and data manipulation. Path planning and image processing computations are typically executed on digital microprocessors. This dissertation explores an evolution of analog signal processing using Field Programmable Analog Arrays (FPAAs); it describes techniques for mapping different solutions onto the hardware, and it describes the benefits and limitations. The motivation is lower power, more capable solutions that also provide better algorithm performance metrics such as time and space complexity. This may be a significant advantage for MAVs, ocean gliders or other robot applications where the power budget for on-board signal processing is limited.

Les activités scientifiques que nous présentons dans ce manuscrit de thèse s’inscrivent dans la thématique de l’intelligence ambiante, axe stratégique ADREAM au sein du LAAS-CNRS. Depuis plusieurs années notre équipe de recherche N2IS fédère l’approche technologique de la SHM avec pour objectif la surveillance de santé structurelle. En effet, la maturité des matériaux innovants tels que les composites suscitent un intérêt certain auprès des constructeurs aéronautiques, ou bien encore l’utilisation des matériaux de type béton pour des ouvrages d’art, sont autant de structures hétérogènes qui nécessitent une surveillance périodique et/ou continue. Ceci, afin de détecter des cracks, des fissures, des corrosions surfaciques ou bien encore des délaminages. Pour ce faire, les solutions existantes s’appuient usuellement sur des technologies de contrôle non destructif (CND) qui intègrent le plus souvent des réseaux de capteurs à faible consommation interfacés avec des systèmes d’analyses des signaux. Ces approches CND présentent des limitations fonctionnelles majeures : elles ne sont pas versatiles et ne permettent pas d’assurer une continuité de service dans un mode « dégradé » lors d’un fonctionnement sur batterie avec un niveau d’énergie minimal. Notre travail de recherche se situe dans une perspective liée à la quantification d’un niveau de robustesse de structure hétérogène. Il a pour ambition le développement et l’intégration de systèmes matériels mixtes (analogiques/numériques) reconfigurables. Au terme d’une investigation sur les principales solutions technologiques matérielles reprogrammables et compte tenu de la problématique liée aux développements d’algorithmes d’analyse embarqués et de la minimisation de la consommation énergétique des capteurs, le choix s’est porté sur des technologies complémentaires FPAA et FPGA. Initialement nos études de recherche se sont focalisées sur l'étude de fonction analogique matérielle reconfigurable analogique. L'objectif est de démontrer une faisabilité conceptuelle en intégrant un système de conditionnement complexe (implémentation d'une technique de détection synchrone), ceci en considérant le compromis entre la prise de décision d’une reconfiguration à la volée vis-à-vis d’une gestion rationnelle de l'énergie du système. Dès lors, se pose la question de comment intégrer et stocker des données nécessaires au développement d’un traitement numérique performant ? Une solution repose sur une approche hybride avec une puce de type Zynq produite par Xilinx et embarquée sur une Zedboard. Cette solution, plus performante qu’une approche PSoC a permis le développement et l’implémentation de techniques de traitement de signal grâce à des outils d'optimisation et de génération de code de haut niveau. Au terme de ce travail de recherche, les résultats obtenus démontrent la validité des concepts mis en œuvre et permettent d'engager dès à présent le développement d’architectures intelligentes de nouvelle génération / Scientific activities described in this PhD thesis are part of the theme of smart environment, strategy axes of ADREAM with the LAAS-CNRS. Since several years, our research team (N2IS) had a field of interest in SHM (Structural Health Monitoring) with the objective of doing a smart diagnostic on different heterogeneous structures. Indeed, the maturity of innovative materials such as composites triggering interest among aircraft manufacturers, or even the use of materials like concrete structures of civil engineering, all those heterogeneous structures that require periodic monitoring and / or continuous one. This is to detect cracks, disbond, surface corrosion or even delamination. To do this, existing solutions usually rely on technologies of nondestructive testing (NDT) that incorporate mostly sensor networks low-power systems interfaced with analysis of signals. These approaches have significant functional limitations: they are not versatile and do not allow for continuity of service in a "degraded" when operating on battery power with a minimum level of energy mode. Our research is a view related to the quantization level of robustness of a heterogeneous structure. Its aim is the development and integration of hardware reconfigurable mixed (A / D ) systems. After an investigation of the main technological solutions reprogrammable hardware and given the problems associated with developments in analytical embedded and minimizing the energy consumption of sensor algorithms. The choice was based on technologies like FPAA and FPGA. Initially our research studies have focused on the study of reconfigurable analog hardware analog. The objective was to show a conceptual feasibility of integrating a complex conditioning system (implementation of a synchronous detection technique), considering the tradeoff between a decision on the fly reconfiguration and a rational energy management system. Therefore, the question of how to integrate and store data necessary for the development of an efficient digital processing. A solution based on a hybrid approach with a chip produced by Xilinx called Zynq and embedded on a Zedboard. This solution is more efficient than a PSoC approach and allowed the development and implementation of signal processing techniques with tools for optimization and provided a solution of self-generation code trough a graphic interface. Following this research, the results obtained demonstrate the validity of the concepts implemented and allow us to imagine the next smart generation architectures

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.

This thesis presents a body of work in the field of reconfigurable and neuromorphic circuits and systems. Three main projects were undertaken. The first was using a Field-Programmable Analog Array (FPAA) to model the cable behavior of dendrites using analog circuits. The second was to design, lay out, and test part of a new FPAA, the RASP 2.9v. The final project was to use floating-gate programming to remove offsets in a neuromorphic FPAA, the RASP Neuron 1D.

With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer high performance given tight constraints on power and chip area. Field programmable arrays utilizing floating-gate technology are one possible solution to analog design. It offers the advantages of analog processing with the additional advantage of reconfigurability, giving the designer the ability to test new analog designs without costly and time-consuming fabrication and test cycles. In this work, a new interface for FPAA's is demonstrated called Sim2spice, with which users can design signal processing systems in Matlab Simulink and compile them to SPICE circuit netlists. These netlists can be further compiled with a tool called GRASPER to a switch list for programming on an FPAA chip. Example library elements are shown, along with some compiled systems such as filters and vector-matrix multipliers. One particularly compelling application of reconfigurable analog design is the field of neuromorphic circuits, which aims to reproduce the basic functional characteristics of biological neurons and synapses in analog integrated circuit technology. Simulink libraries have been built to allow designers to build neuromorphic systems on several FPAAs that have been developed expressly for the purpose of building neurons and connecting them in networks with synapses. Several possible dynamically learning synapses have also been explored.