ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / This paper describes the Flexible Telemetry Transceiver (FNT)-a modular, scalable, standards-based, software configurable, microwave wireless telemetry network transceiver. The FNT enables flexible, high-rate, long-range, duplex, network services across multipoint to multipoint wireless channel.

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs.

Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar to the FPGAs of the digital domain. Like FPGAs, FPAAs can help reduce the time and money costs of the integrated circuit design cycle and make analog design much easier. In recent years, several types of FPAAs have been developed. Among these, FPAAs that use floating-gate transistors as programming elements have shown great potential in scalability because of the simplicity they provide in configuring the chip. Existing tools for programming FPAAs tend to be device specific and aimed at specific tasks such as filter design. To move FPAAs to the next step, more powerful and generic placement and routing tools are necessary. This thesis presents a placement and routing tool for large-scale floating-gate-based FPAAs. A topology independent routing resource graph (RRG) was used to model the FPAA routing topology, which enables generic description of any FPAA architecture with arbitrary connectivity including possible FPGA support in the future as well. So far, different FPAA architectures have been specified and routed successfully. The tool is already in use in classes and workshops for analog circuit and system design. Efficient ways to describe circuits and user constraints were developed to allow easy integration with other tools. Analog circuit performance was optimized by taking into account the routing parasitic effects on interconnects under various device-related constraints. Parasitic modeling allows simulation and evaluation of circuits routed on FPAA. Finally, a methodology was developed to explore the optimum architecture for a set of circuit classes by evaluating the efficiency of different architectures for each circuit class.

Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.

The Cooperative Analog/Digital Signal Processing (CADSP) research group's approach to signal processing is to see what opportunities lie in adjusting the line between what is traditionally computed in digital and what can be done in analog. By allowing more computation to be done in analog, we can take advantage of its low power, continuous domain operation, and parallel capabilities. One setback keeping Analog Signal Processing (ASP) from achieving more wide-spread use, however, is its lack of programmability. The design cycle for a typical analog system often involves several iterations of the fabrication step, which is labor intensive, time consuming, and expensive. These costs in both time and money reduce the likelihood that engineers will consider an analog solution. With CADSP's development of a reconfigurable analog platform, a Field-Programmable Analog Array (FPAA), it has become much more practical for systems to incorporate processing in the analog domain. In this Thesis, I present an entire chain of tools that allow one to design simply at the system block level and then compile that design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks, covering a broad range of functions from matrix computation to interfacing. In addition to these tools and blocks, the most recent FPAA architectures are discussed. These include the latest RASP general-purpose FPAAs as well as an adapted version geared toward high-speed applications.

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

Neste trabalho o teste de dispositivos analógicos programáveis é abordado. Diversas metodologias de teste analógico existentes são estudadas e algumas delas são utilizadas nas estratégias desenvolvidas. Dois FPAAs (Field Programmable Analog Arrays) comerciais de fabricantes e modelos distintos são utilizados para validar as estratégias de teste propostas. O primeiro dispositivo estudado é um FPAA de tempo contínuo (capaz de implementar circuitos contínuos no tempo) da Lattice Semiconductors. Tal dispositivo é marcado pela característica estrutural de sua programabilidade. Por esta razão, a estratégia a ele aplicada é baseada em um método de teste também estrutural, conhecido como OBT (Oscillation-Based Test). Neste método o circuito é dividido em blocos simples que são transformados em osciladores. Os parâmetros do sinal obtido, tais como a freqüência de oscilação e a amplitude, têm relação direta com os componentes utilizados na implementação do oscilador. Desta maneira, é possível detectar falhas no FPAA observando os parâmetros do sinal gerado. Esta estratégia é estudada inicialmente considerando uma análise externa dos parâmetros do sinal. Como uma alternativa de redução de custos e melhoria na cobertura de falhas, um analisador de resposta baseado em um duplo integrador é adotado, permitindo que a avaliação do sinal gerado pelo oscilador seja feita internamente, utilizando-se os recursos programáveis do próprio FPAA. Os resultados obtidos para as análises interna e externa são então comparados. O segundo FPAA estudado, da Anadigm Company, é um dispositivo a capacitores chaveados que tem como característica a programabilidade funcional. Por esta razão o desenvolvimento de uma técnica de teste estrutural é dificultado, pois não se conhece detalhes da arquitetura do componente. Por esta razão, uma técnica de teste funcional, conhecida como Transient Response Analysis Method, é aplicada ao teste deste FPAA. Neste método o circuito sob teste é dividido em blocos funcionais de primeira e segunda ordem e a resposta transiente destes blocos para um dado estímulo de entrada é analisada. O bloco sob teste é então duplicado e um esquema de auto-teste integrado baseado em redundância é desenvolvido, com o intuito de se obter um sinal de erro. Este sinal de erro representa a diferença das respostas transientes dos blocos duplicados. Como proposta para se aumentar a observabilidade do sinal de erro o mesmo é integrado ao longo tempo, aumentando a capacidade de detecção de falhas quando utilizado este método. Em ambas estratégias o objetivo principal do trabalho é testar os blocos analógicos programáveis dos FPAAs explorando ao máximo a programabilidade dos dispositivos e utilizando recursos pré-existentes para auxiliar no teste. Os resultados obtidos mostram que as estratégias desenvolvidas configuram boas alternativas para o auto-teste integrado deste tipo de componente. / This work addresses the test of programmable analog devices. Several analog test methodologies are studied and some of them are applied in the developed strategies. In order to validate these strategies, two commercial FPAAs (Field Programmable Analog Arrays), of different vendors and distinct models, are considered as devices under test. The first studied device is a continuous-time FPAA from Lattice Semiconductors. One important characteristic of such device is the structural programmability. For this reason the test strategy applied to this FPAA is based in a structural method known as OBT (Oscillation-Based Test). In this method, blocks of the circuit under test are individually converted into oscillators. The parameters of the generated signal, such as the frequency and amplitude, can be expressed as function of the components used in the oscillator implementation. This way, it is possible to detect faults in the FPAA simply observing such parameters. This method is firstly studied considering an external analysis of the signal parameters. However, in a second moment, an internal response analyzer, based on a double integrator, is built with the available programmable resources of the FPAA. This way, overall test cost is reduced, while the fault coverage is increased with no area overhead. The obtained results considering the external analysis and the built-in response evaluation are compared. The second considered FPAA, from Anadigm Company, is a switched capacitor device whose programming characteristic is strictly functional. Thus, a structural test method cannot be easily developed and applied without the previous knowledge of he device architectural details. For this reason, a functional test method known as TRAM (Transient Response Analysis Method) is adopted. In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks for a given input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between the fault-free and faulty Configurable Analog Blocks (CABs). As a proposal to augmenting the observability, the error signal is integrated, enhancing de fault detection capability when using this method. In both developed strategies the main objective is to test the CABs of the FPAAs exploiting the device programmability, using the existing resources in order to aid the test. The obtained results show that the developed strategies represent good alternatives to the built-in self-test of such type of device.

Memristor is a novel passive electronic device and a promising candidate for new generation non-volatile memory and analog computing. Analog computing based on memristors has been explored in this study. Due to the lack of commercial electrical testing instruments for those emerging devices and crossbar arrays, we have designed and built testing circuits to implement analog and parallel computing operations. With the setup developed in this study, we have successfully demonstrated image processing functions utilizing large memristor crossbar arrays. We further designed and experimentally demonstrated the first memristor based field programmable analog array (FPAA), which was successfully configured for audio equalizer and frequency classifier demonstration as exemplary applications of such memristive FPAA (memFPAA).

Essa tese tem como objeto de estudo a história do Instituto de Arquitetos do Brasil entre 1920 e 1970, buscando compreender o lugar que a entidade ocupou no meio profissional brasileiro e as redes institucionais de diálogo que teceu em âmbito nacional e internacional ao longo do período. Com isso, pretende discutir seu papel para a construção coletiva de uma nova sociabilidade profissional, para o estabelecimento de laços efetivos de troca e para a elaboração, afirmação e difusão de ideários e práticas arquitetônicas e urbanísticas. A narrativa foi organizada em três capítulos, sobrepostos em seu recorte cronológico, que buscam pensar essas tramas institucionais costuradas pelo IAB em seus distintos alcances: nacional, americano e global, respectivamente. / This thesis aims to study the history of the Institute of Architects of Brazil between 1920 and 1970, trying to understand the place that the entity occupied in the Brazilian professional circles and the institutional networks of dialogue that developed at national and international level throughout the period. It intends to discuss the Institute\'s role for the collective construction of a new professional network, for the establishment of effective communication ties and for the creation, assertion and diffusion of architectonic and urbanistic ideas and practices. The narrative was organized in three chapters with a common chronological boundary, striving to analyze these networks built by the IAB in their different scopes: national, American and global, respectively.