Dans cette thèse, nous nous intéressons à la résolution de quelques problèmes d'optimisation combinatoires que nous avons choisi de traiter en deux volets. Dans un premier temps, nous étudions des problèmes d'optimisation issus de l'ordonnancement d'un ensemble de tâches sur des machines de calcul et où on cherche à minimiser l'énergie totale consommée par ces machines tout en préservant une qualité de service acceptable. Dans un deuxième temps, nous traitons deux problèmes d'optimisation classiques à savoir un problème d'ordonnancement dans une architecture de machines parallèles avec des temps de communication, et un problème de placement de données dans des graphes modélisant des réseaux pair-à-pair et visant à minimiser le coût total d'accès aux données. / In this thesis, we focus on solving some combinatorial optimization problems that we have chosen to study in two parts. Firstly, we study optimization problems issued from scheduling a set of tasks on computing machines where we seek to minimize the total energy consumed by these machines while maintaining acceptable quality of service. In a second step, we discuss two optimization problems, namely a classical scheduling problem in architecture of parallel machines with communication delays, and a problem of placing data in graphs that represent peer-to-peer networks and the goal is to minimize the total cost of data access.

"Product Placement" or "Brand Placement" is the paid inclusion of branded products or brand identifiers, through audio and/or visual means, within entertainment media. This dissertation is a collection of three essays that investigate factors affecting the effectiveness of product placements. The first essay focuses on two measures of product placement effectiveness - audience recall and attitudes toward the placement. Extant empirical studies that address the antecedents of these constructs were integrated through a meta-analysis. Some key findings are as follows. The prominence of placements is a controllable executional factor that was found to have a significant positive relationship with recall. Recall was also affected by modality - audio-visual placements had better recall than audio-only placements which in turn performed better than visual-only placements. Audience attitudes toward placements had a strong relationship with the nature of the product - products that had negative ethical connotations were found to be less acceptable to audiences. However, viewers who were avid consumers of entertainment media tended to have more positive attitudes. Essay 2 focuses on the effect of repetition of placements of the same brand within a single television program. The results from an experiment show that unlike advertising, there was no negative-U relationship between the frequency of placements and audience attitudes toward the brand placed. In the case of visual placements, attitudes actually improved with frequency as a result of the mere exposure effect. However, this effect was not observed in the case of audio placements. Essay 3 addresses "Need for Cognition", an individual level variable that was found to affect audience response toward the brand placed. Data were collected through an online survey and analyzed using structural equation modeling. The mood of the viewer and their parasocial attachment with the character in the program that was associated with the placement had significant positive relationships with their attitude toward the specific placement, which in turn had a strong positive relationship with the attitude toward the brand. However, the latter relationship was moderated by NFC, with the effect being significantly stronger for those viewers who did not engage in, or enjoy analytical activity. Limitations of the studies, the relevance of the findings to marketing practice, and the contribution to scholarly research are discussed.

Structured ASICs provide an exciting middle-ground between ASIC and FPGA design styles because they provide trade-off between the high per- formance of ASIC design and low costs of FPGA design. To fully utilize the benefits of structured ASIC, placement stage must be aware of the modularity of the structured ASIC architecture. This work describes a novel solution to placement of structured ASICs. Integer linear programming formulation is proposed for satisfying the constraints associated with structured ASIC clock architecture. Regularity of the platform is exploited during legalization and wirelength recovery stages to speed-up the detailed placement stage. Our methods show overall wirelength reduction up to 33% and up to 3X speedup compared to other placers. / text

One of the major drawbacks of reprogrammable microchips, such as field-programmable gate arrays (FPGAs), is an inherent speed disadvantage over ASIC technologies. To mitigate this speed disadvantage, this thesis presents a novel algorithm to improve timing performance at the possible expense of area and runtime. The algorithm presented leverages node duplication and a depth-optimal initial clustering to provide a starting point for a non-greedy, iterative optimization technique using detailed placement and timing information to develop the final clustering and placement solutions. For a set of benchmarks commonly used in FPGA research, the proposed algorithm achieves an 11\% critical-path delay improvement compared to the VPR academic tool flow. This performance improvement is obtained at the expense of a 44\% increase in area usage and a 26x increase in maximum runtime. Techniques have also been implemented to sacrifice performance to moderate the area or runtime increases. For a 1\% critical-path delay penalty, the runtime can be improved by a factor of 4. The algorithm also provides facilities to impose area restrictions, in which case timing degradation is proportional to the area saved.

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ABSTRACT The major purpose of the study is to explore the viewpoints about the issues related to the placement of elementary and junior high school principals in Taiwan. The issues include the advantages or defects of the principal placement system, the formation of the principal placement committee, the implementation of the principal placement action, the qualifications and the criterion of the principal placement, and the arrangement of those who fail to be principals to become teachers again. The study, based on the literature review, designed a questionnaire about these issues related to the placement of elementary and junior high school principals in Taiwan. The objects of questionnaire survey include administrators of educational department, members of education committee in the councils, principals, managers, teachers and parents of elementary and junior high schools, which are randomly selected in eight cities. There are a total of 645 respondents. According to results of the study, some suggestions are made for education administration and future studies.

One of the major drawbacks of reprogrammable microchips, such as field-programmable gate arrays (FPGAs), is an inherent speed disadvantage over ASIC technologies. To mitigate this speed disadvantage, this thesis presents a novel algorithm to improve timing performance at the possible expense of area and runtime. The algorithm presented leverages node duplication and a depth-optimal initial clustering to provide a starting point for a non-greedy, iterative optimization technique using detailed placement and timing information to develop the final clustering and placement solutions. For a set of benchmarks commonly used in FPGA research, the proposed algorithm achieves an 11\% critical-path delay improvement compared to the VPR academic tool flow. This performance improvement is obtained at the expense of a 44\% increase in area usage and a 26x increase in maximum runtime. Techniques have also been implemented to sacrifice performance to moderate the area or runtime increases. For a 1\% critical-path delay penalty, the runtime can be improved by a factor of 4. The algorithm also provides facilities to impose area restrictions, in which case timing degradation is proportional to the area saved.

Zugl.: München, Munich Business School, Diplomarbeit, 2006.

Zugl.: München, Munich Business School, Diplomarbeit, 2006

One of the major drawbacks of reprogrammable microchips, such as field-programmable gate arrays (FPGAs), is an inherent speed disadvantage over ASIC technologies. To mitigate this speed disadvantage, this thesis presents a novel algorithm to improve timing performance at the possible expense of area and runtime. The algorithm presented leverages node duplication and a depth-optimal initial clustering to provide a starting point for a non-greedy, iterative optimization technique using detailed placement and timing information to develop the final clustering and placement solutions. For a set of benchmarks commonly used in FPGA research, the proposed algorithm achieves an 11\% critical-path delay improvement compared to the VPR academic tool flow. This performance improvement is obtained at the expense of a 44\% increase in area usage and a 26x increase in maximum runtime. Techniques have also been implemented to sacrifice performance to moderate the area or runtime increases. For a 1\% critical-path delay penalty, the runtime can be improved by a factor of 4. The algorithm also provides facilities to impose area restrictions, in which case timing degradation is proportional to the area saved. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate