Thesis (M.S.)--Worcester Polytechnic Institute. / Includes bibliographical references (leaves 106-107).

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 81-83). Also available via the Internet.

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. The use of a runtime resource allocation environment modelled on a classical software operating system would allow the full benefits of dynamic reconfiguration on high density FPGAs to be realised. In addition to runtime resource allocation, other services provided by an operating system such as abstraction of I/O and inter-application communication would provide additional benefits to the users of a reconfigurable computer. This could possibly reduce the difficulty of application development and deployment. In this thesis, an operating system for reconfigurable computing that supports dynamically arriving applications is presented. This is achieved by firstly developing the abstractions with which designers implement their applications and a set of algorithm requirements that specify the resource allocation and logic partitioning services. By combining these, an architecture of an operating system for reconfigurable computing can be specified. A prototype implementation on one platform with multiple applications is then presented which enables an exploration of how the resource allocation algorithms interact amongst themselves and with typical applications. Results obtained from the prototype include the measurement of the performance loss in applications, and the time overheads introduced due to the use of the operating system. Comparisons are made with programmable logic applications run with and without the operating system. The results show that the overheads are reasonable given the current state of the technology of FPGAs. Formulas for predicting the user response time and application throughput based on the fragmentation of an FPGA are then derived. Weaknesses are highlighted in the current design flows and the architecture of current FPGAs must be rectified if an operating system is to become main-stream. For the tool flows this includes the ability to pre-place and pre-route cores and perform high speed runtime routing. For the FPGAs these include an optimised network, a memory management core, and a separate layer to handle dynamic routing of the network. / thesis (PhD)--University of South Australia, 2005.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 212-225). Available also in a digital version from Dissertation Abstracts.

Not available / text

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. / Thesis (PhD)--University of South Australia, 2005.

Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. The use of a runtime resource allocation environment modelled on a classical software operating system would allow the full benefits of dynamic reconfiguration on high density FPGAs to be realised. In addition to runtime resource allocation, other services provided by an operating system such as abstraction of I/O and inter-application communication would provide additional benefits to the users of a reconfigurable computer. This could possibly reduce the difficulty of application development and deployment. In this thesis, an operating system for reconfigurable computing that supports dynamically arriving applications is presented. This is achieved by firstly developing the abstractions with which designers implement their applications and a set of algorithm requirements that specify the resource allocation and logic partitioning services. By combining these, an architecture of an operating system for reconfigurable computing can be specified. A prototype implementation on one platform with multiple applications is then presented which enables an exploration of how the resource allocation algorithms interact amongst themselves and with typical applications. Results obtained from the prototype include the measurement of the performance loss in applications, and the time overheads introduced due to the use of the operating system. Comparisons are made with programmable logic applications run with and without the operating system. The results show that the overheads are reasonable given the current state of the technology of FPGAs. Formulas for predicting the user response time and application throughput based on the fragmentation of an FPGA are then derived. Weaknesses are highlighted in the current design flows and the architecture of current FPGAs must be rectified if an operating system is to become main-stream. For the tool flows this includes the ability to pre-place and pre-route cores and perform high speed runtime routing. For the FPGAs these include an optimised network, a memory management core, and a separate layer to handle dynamic routing of the network. / thesis (PhD)--University of South Australia, 2005.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

No description available.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 124-135). Available also in a digital version from Dissertation Abstracts.