Spelling suggestions: "subject:"date array circuits"" "subject:"rate array circuits""
11 |
Characterization and reliability of HFO₂ and hfsion gate dielectrics with tin metal gateKrishnan, Siddarth A. 28 August 2008 (has links)
Not available / text
|
12 |
Charge trapping effects on mobility and threshold voltage instability in high-k gate stacksSim, Jang Hoan 28 August 2008 (has links)
Not available / text
|
13 |
High-permittivity dielectrics and high mobility semiconductors for future scaled technology: Hf-based High-K gate dielectrics and interface engineering for HfO₂/Ge CMOS deviceLu, Nan 28 August 2008 (has links)
Not available / text
|
14 |
Technology development and process integration of alternative gate dielectric material : hafnium oxide /Lee, Byoung Hun, January 2000 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 123-134). Available also in a digital version from Dissertation Abstracts.
|
15 |
Characterization and reliability of HFO₂ and hfsion gate dielectrics with tin metal gateKrishnan, Siddarth A., January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.
|
16 |
Charge trapping effects on mobility and threshold voltage instability in high-k gate stacksSim, Jang Hoan. January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.
|
17 |
High-permittivity dielectrics and high mobility semiconductors for future scaled technology Hf-based High-K gate dielectrics and interface engineering for HfO₂/Ge CMOS device /Lu, Nan, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.
|
18 |
Gate level coverage of a behavioral test generatorBaweja, Gunjeetsingh 10 November 2009 (has links)
Use of traditional gate level test generation techniques is prohibitively expensive and time consuming for VLSI chips. High level approaches to test generation have been proposed to improve the efficiency of test generation, e.g., the Behavioral Test Generator developed at Virginia Tech generates test vectors from high level Behavioral VHDL descriptions. To validate the utility of these test vectors, it needs to be established that they provide adequate coverage at the gate level. This thesis shows that test vectors obtained from the Behavioral Test Generator provide adequate coverage for the equivalent gate level circuit. A system that was developed to effectively evaluate the test vectors is presented. The implementation of Heuristic Test Generator to improve the coverage of the Behavioral Test Generator is explained. / Master of Science
|
19 |
A tool kit for the design of superconducting programmable gate arraysFourie, Coenrad Johann 12 1900 (has links)
Thesis (PhD)--University of Stellenbosch, 2003. / ENGLISH ABSTRACT: The development of a tool kit for the design of superconducting programmable gate
arrays (SPGAs) is discussed. A circuit optimizer using genetic algorithms is developed
and evaluated. Techniques and a program are also developed for the generation of
segmentized 3D models with which to calculate inductance in circuit structures through
FastHenry. The ability to add random variations to the dimensions of the models is
included. These tools are then used to design novel latching elements that allow the
construction of reprogrammable Rapid Single Flux Quantum (RSFQ) circuits. A circular
process is used, whereby layouts are converted back to circuit diagrams through element
extraction, and reoptimized if necessary. Two programmable frequency dividers are then
designed; one for testing the routing and switch structures and programming architecture
of an SPGA, and another compact one for testing the latching elements and off-chip
interface. The dissertation concludes with an overview of the circuits necessary for the
implementation of a fully functional SPGA. / AFRIKAANSE OPSOMMING: Die ontwikkeling van ’n gereedskapstel vir die ontwerp van supergeleier FPGA’s
(SPGA’s) word bespreek. Eerstens word ’n stroombaanoptimeerder, wat met genetiese
algoritmes funksioneer, ontwikkel en geëvalueer. Daarna word tegnieke en ’n program
ontwikkel om driedimensionele segmentmodelle te genereer waaruit FastHenry die
induktansie van stroombaanstrukture kan bepaal. Die vermoë om toevalsveranderinge by
die dimensies van die modelle te voeg, is ook ingesluit. Hierdie gereedskap word dan
gebruik om nuwe grendelelemente te ontwerp waarmee herprogrammeerbare Rapid
Single Flux Quantum (RSFQ) stroombane gebou kan word. ’n Sirkulêre proses word
gevolg, waarvolgens uitlegte na stroombaandiagramme teruggeskakel kan word (deur
elementonttrekkings) en, indien nodig, heroptimeer kan word. Twee programmeerbare
frekwensiedelers word daarna ontwerp; een om die pulsvervoer- en skakelstrukture,
asook programmeringsargitektuur van ’n SPGA te toets, en ’n ander, kompakter een om
die grendelelemente en warmlogika koppelvlakke mee te toets. Die proefskrif sluit af met
’n oorsig oor die stroombane benodig vir die implementering van ’n volledig funksionele
SPGA.
|
20 |
Power losses and thermal modeling of a voltage source inverterOberdorf, Michael Craig. 03 1900 (has links)
This thesis presents thermal and power loss models of a three phase IGBT voltage source inverter used in the design of the 625KW fuel cell and reformer demonstration which is a top priority for the Office of Naval Research. The ability to generate thermal simulations of systems and to accurately predict a system's response becomes essential in order to reduce the cost of design and production, increase reliability, quantify the accuracy of the estimated thermal impedance of an IGBT module, predict the maximum switching frequency without violating thermal limits, predict the time to shutdown on a loss of coolant casualty, and quantify the characteristics of the heat-sink needed to dissipate the heat under worst case conditions. In order to accomplish this, power loss and thermal models were created and simulated to represent a three phase IGBT voltage source inverter in the lab. The simulated power loss and thermal model data were compared against the experimental data of a three phase voltage source inverter set up in the Naval Postgraduate School power systems laboratory.
|
Page generated in 0.0672 seconds