Before 1971, all the electronics were based on three basic circuit elements. Until a professor from UCBerkeley reasoned that another basic circuit element exists, which he called memristor; characterized bythe relationship between the charge and the flux-linkage. A memristor is essentially a resistor withmemory. The resistance of a memristor (memristance) depends on the amount of current that is passingthrough the device. In 2008, a research group at HP Labs succeeded to build an actual physical memristor. HP's memristorwas a nanometer scale titanium dioxide thin film, composed of two doped and undoped regions,sandwiched between two platinum contacts. After this breakthrough, a huge amount of research startedwith the aim of better realization of the device and discovering more possible applications of thememristor. In this report, it is attempted to cover a proper amount of information about the history, introduction,implementation, modeling and applications of the device. But the main focus of this study is onmemristor modeling. Four papers on modeling of the memristor were considered, and since there wereno cadence models available in the literature at the time, it was decided to develop some cadencemodels. So, cadence models from the mentioned papers were designed and simulated. From the samemodeling papers some veriloga models were written as well. Unfortunately, due to some limitation of thedesign tool, some of the models failed to provide the expected results, but still the functioning modelsshow satisfactory results that can be used in the circuit simulations of memristors.

Non-volatile memory (NVM) is a form of computer memory in which the logical value (1 or 0) of a bit is retained when the computer is in its’ powered off state. Flash memory is a major form of NVM found in many computer-based technologies today, from portable solid state drives to numerous types of electronic devices. The popularity of flash memory is due in part to the successful development and commercialization of the floating gate transistor. However, as the floating gate transistor reaches its’ limits of performance and scalability, viable alternatives are being aggressively researched and developed. One such alternative is a memristor-based memory application often referred to as ReRAM or RRAM (Resistive Random Access Memory). A memristor (memory resistor) is a passive circuit element that exhibits programmable resistance when subjected to appropriate current levels. A high resistance state in the memristor corresponds to a logical ‘0’, while the low resistance state corresponds to a logical ‘1’. One memristive system currently being actively investigated is the metal/metal oxide/metal material stack in which the metal layers serve as contact electrodes for the memristor with the metal oxide providing the variable resistance functionality. Application of an appropriate potential difference across the electrodes creates oxygen vacancies throughout the thickness of the metal oxide layer, resulting in the formation of filaments of metal ions which span the metal oxide, allowing for electronic conduction through the stack. Creation and disruption of the filaments correspond to low and high resistance states in the memristor, respectively. For some time now, HfO2 has been researched and developed to serve as a high-k material for use in high performance CMOS MOSFETs. As it happens, HfO2-based RRAM devices have proven themselves as viable candidates for NVM as well, demonstrating high switching speed (< 10 ns), large OFF/ON ratio (> 100), good endurance (> 106 cycles), long lifetime, and multi-bit storage capabilities. HfO2-based RRAM is also highly scalable, having been fabricated in cells as small as 10 x 10 nm2 while still maintaining good performance. Previous work examining switching properties of micron scale HfO2-based RRAM has been performed by the Vogel group. However, a viable process for fabrication of nano-scale RRAM is required in order to continue these studies. In this work, a fabrication process for nano-scale cross-point TiN/ HfO2/TiN RRAM devices will be developed and described. Materials processing challenges will be addressed. The switching performance of devices fabricated by this process will be compared to the performance of similar devices from the literature in order to confirm process viability.

Master of Science / Department of Electrical and Computer Engineering / Stephen A. Dyer / Every person with an electronics background will be familiar with the three fundamental circuit elements—the resistor, the capacitor, and the inductor.These three elements are defined by the relation between two of the four fundamental circuit variables—current, voltage, charge and flux.In 1971, Leon Chua reasoned on the grounds of symmetry that there should be a fourth fundamental circuit element which gives the relationship between flux and charge.He named this circuit element the memristor, which is short for―"memory resistor."In May 2008, researchers at HP Labs published a paper announcing a model for the physical realization of the memristor. This report focuses on the memristor and reviews its properties.The HP model for the memristor is also discussed, and its behavior is studied through simulations.A few of the potential applications of the memristor are presented.

With conventional CMOS technologies approaching their scaling limits, researchers are actively investigating alternative technologies for ever increasing computing and mobile demand. A number of different technologies are currently being studied by different research groups. In the last decade, one-dimensional (1D) carbon nanotubes (CNT), graphene, which is a two-dimensional (2D) natural occurring carbon rolled in tubular form, and zero-dimensional (0D) fullerenes have been the subject of intensive research. In 2008, HP Labs announced a ground-breaking fabrication of memristors, the fourth fundamental element postulated by Chua at the University of California, Berkeley in 1971. In the last few years, the memristor has gained a lot of attention from the research community. In-depth studies of the memristor and its analog behavior have convinced the community that it has the potential in future nano-architectures for optimization of high-density memory and neuromorphic computing architectures. The objective of this thesis is to explore memristors for analog and mixed-signal system design using Simscape. This thesis presents a memristor model in the Simscape language. Simscape has been used as it has the potential for modeling large systems. A memristor based programmable oscillator is also presented with simulation results and characterization. In addition, simulation results of different memristor models are presented which are crucial for the detailed understanding of the memristor along with its properties.

In dieser Arbeit werden Quantenpunkt-Speichertransistoren basierend auf modulationsdotierten GaAs/AlGaAs Heterostrukturen mit vorpositionierten InAs Quantenpunkten vorgestellt, welche in Abhängigkeit der Ladung auf den Quantenpunkten unterschiedliche Widerstände und Kapazitäten aufweisen. Diese Ladungsabhängigkeiten führen beim Anlegen von periodischen Spannungen zu charakteristischen, durch den Ursprung gehenden Hysteresen in der Strom-Spannungs- und der Ladungs-Spannungs-Kennlinie. Die ladungsabhängigen Widerstände und Kapazitäten ermöglichen die Realisierung von neuromorphen Operationen durch Nachahmung von synaptischen Funktionalitäten und arithmetischen Operationen durch Integration von Spannungs- und Lichtpulsen. / In this thesis, state-dependent resistances and capacitances in quantum dot floating gate transistors based on modulation doped GaAs/AlGaAs heterostructures with site-controlled InAs quantum dots are presented. The accumulation of electrons in the quantum dots simultaneously increases the resistance and decreases the capacitance, which leads to characteristic pinched hysteresis loops in the current-voltage- and the charge-voltage-characteristics when applying periodic input signals. The concurrent resistance and capacitance switching enables the realization of neuromorphic operations via mimicking of synaptic functionalities and arithmetic operations via the integration of voltage and light pulses.

Low dimensional semiconductors are promising materials with diverse range of applications in a variety of fields. Specifically, in recent times low dimensional oxide and sulfide based semiconductors are regarded as materials that can have potential applications in chemical gas sensor, optoelectronic devices and memristor. How ever, in some cases it is envisioned that appropriate doping as well as phase stabilization is important in enhancing their material properties. This work presents the synthesis, characterization and application of various (pristine and doped) quasi-one dimensional metal oxides (TiO2, VO2) and two-dimensional materials (CuO thin film, MoS2). Some practical protocols for stabilization of specific phases at ambient conditions via a new method of doping in VO2 nanostructures with aluminum, is demonstrated. Similarly, a temperature-doping level phase diagram for the free-standing nanostructures in the temperature range close to the ambient conditions was presented. TiO2 nanowire was doped during growth and electrical measurements on individual TiO2 single crystal nanowires indicate that light in visible range can induce electron-hole pair formation. Furthermore, gas sensing (CO, H2) measurements taken under visible light irradiation imply that photo-activated chemical oxidization on the surface of TiO2 nanowires occurs, which is responsible for the observed measurements. Further, the effect of self heating in some nanostructures was also explored. Since self-heating is a prospective power-efficient energy delivery channel to the conductometric chemical sensors that require elevated temperatures for their operation, the unprecedentedly low power consumption can be achieved via minimizing the heat dissipation in the optimized device architecture. By investigating the heat dissipation in these devices we show that the thermal, electrical and chemical properties of the self-heated semiconducting nanowires appear to be strongly coupled with each other at nanoscale. This opens up unique opportunity to fabricate low power nanoscopic sensing leading to an ultra-small and power efficient single nanostructure gas recognition system. The CuO film based lateral devices were fabricated and studied for its resistive switching behavior. A good, stable and reproducible threshold RS performance of CuO film was obtained by electrical measurement. Finally, the micro-flake MoS2 based FET photoelectronic device was fabricated (using mechanically exfoliated MoS2) and its electronic and photoelectronic properties were investigated. We show that though the FET mobility values of MoS2 microflake is in the average range, but the photo-responsivity is much higher compared to most of others similar sulfide based 2D layered materials.

AN ABSTRACT OF THE THESIS OFAPARNA REDDY KOTTE, for the Master of science degree in Electrical and Computer Engineering, presented on November 5,2020, at Southern Illinois University Carbondale. TITLE: MEMRISTOR BASED SRAM MAJOR PROFESSOR: Dr. Haniotokis Themistoklis The easy usage and less standby leakage are the main reasons SRAMs are mostly used for mobile applications both on chip and off chip memories. Various SRAM cells have been under research for many years. In post-CMOS era, rising of memristor technology is expected to be a key driver due to its outstanding features to replace the present memory technologies. Memristor is a non-volatile component that memorizes the proportion of current passed through it, reserving the data in the form of resistance. With its non-volatile characteristics, ultra-low power consumption, higher density capability, fast operating speed, ability to function as a multi-level cell and good scalability and compatibility with CMOS technology, memristor technology is found to be best to replace the SRAM cells. Memristor based SRAM cell can be an efficient circuit component that is being proposed in this thesis which consumes less power and allows the conventional SRAM cell to retain data with lesser number of transistors at power-down without any auxiliary circuit. This thesis contains the operating procedure and simulated results of the proposed four transistor and two memristor SRAM using 90nm technology performed on Cadence Virtuoso tool.

Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for resistive-based memory systems and neural computing. For gateless arrays, we present multiport array structure and readout technique, which for the first time introduces a closed-form solution for the challenging crossbar sneak-paths problem. Moreover, a new adaptive threshold readout methodology is proposed, which employs the memory hierarchy locality property in order to improve the access time to the memristor crossbar. Another fast readout technique based on binary counters is presented for locality-less crossbar systems. On the other hand, for gated arrays, we present new readout technique and circuitry that combines the advantages of the gated and gateless memristor arrays, namely the high-density and low-power consumption. In general, the presented structures and readout methodologies empower much faster and power efficient access to the high-density memristive crossbar, compared to other works presented in the literature. Finally, at the circuit level, we propose novel reactance-less oscillators based on memristor devices, which find promising applications in embedded systems and bio-inspired computing. Altogether, we believe that our contributions to the emerging technology help to push it to the next level, shortening the path towards better futuristic computing systems.

An extensive reliance on technology, an abundance of data, and increasing processing requirements have imposed severe challenges on computing and data processing. Moreover, the roadmap for scaling electronic components faces physical and reliability limits that hinder the utilization of the transistors in conventional systems and promotes the need for faster, energy-efficient, and compact nano-devices. This work thus capitalizes on emerging non-volatile memory technologies, particularly the memristor for steering novel design directives. Moreover, aside from the conventional deterministic operation, a temporal variability is encountered in the devices functioning. This inherent stochasticity is addressed as an enabler for endorsing the stochastic electronics field of study. We tackle this approach of design by proposing and verifying a statistical approach to modelling the stochastic memristors behaviour. This mode of operation allows for innovative computing designs within the approximate computing and beyond Von-Neumann domains. In the context of approximate computing, sacrificing functional accuracy for the sake of energy savings is proposed based on inherently stochastic electronic components. We introduce mathematical formulation and probabilistic analysis for Boolean logic operators and correspondingly incorporate them into arithmetic blocks. Gate- and system-level accuracy of operation is presented to convey configurability and the different effects that the unreliability of the underlying memristive components has on the intermediary and overall output. An image compression application is presented to reflect the efficiency attained along with the impact on the output caused by the relative precision quantification. In contrast, in neuromorphic structures the memristors variability is mapped onto abstract models of the noisy and unreliable brain components. In one approach, we propose using the stochastic memristor as an inherent source of variability in the neuron that allows it to produce spikes stochastically. Alternatively, the stochastic memristors are mapped onto bi-stable stochastic synapses. The intrinsic variation is modelled as added noise that aids in performing the underlying computational tasks. Both aspects are tested within a probabilistic neural network operation for a handwritten MNIST digit recognition application. Synaptic adaptation and neuronal selectivity are achieved with both approaches, which demonstrates the savings, interchangeability, robustness, and relaxed design space of brain-inspired unconventional computing systems.

There is an increased interest in the Conductive Bridge Random Access Memory (CBRAM) and Resistive Random Access Memory (RRAM) because of their excellent scaling potential, low power consumption, high switching speed, good retention and endurance properties. Although, various mechanisms have been proposed to explain the switching behavior in CBRAM devices, i.e. metal ion migration and subsequent formation and rupture of conductive filament, formation of conductive path via oxygen ion transport etc, there are still many aspects of these mechanisms that are little understood or are being disputed. This work probes the details of the switching mechanisms on a new level and asks questions like: 1) How is the formation of nanofilament affected by various degrees of Cu diffusion stopping power of the inert electrode? To answer this question, resistive switches with very thin Cu layers covering the Pt electrode were fabricated and analyzed. 2) How does a limited source of active ions impact the formation and rupture of nanofilaments? To answer this question, new samples with limited Cu supply were fabricated and analyzed. 3) What is the mechanism of nanofilament formation in Pt/TaOx/Pt resistive switches where the active copper electrode is removed and replaced by inert Pt electrode. 4) What are the most suitable conditions (material structure of the device and operation conditions) to set and reset multi nanofilaments? This work summarizes the current status of analysis of the data obtained while attempting to explain interesting phenomena like volatile switching and multiple filament formation experienced by modifying the switch structures. / Master of Science