In the era of Internet of Things and Big Data, unconventional techniques are rising to accommodate the large size of data and the resource constraints. New computing structures are advancing based on non-volatile memory technologies and different processing paradigms. Additionally, the intrinsic resiliency of current applications leads to the development of creative techniques in computations. In those applications, approximate computing provides a perfect fit to optimize the energy efficiency while compromising on the accuracy. In this work, we build probabilistic adders based on stochastic memristor. Probabilistic adders are analyzed with respect of the stochastic behavior of the underlying memristors. Multiple adder implementations are investigated and compared. The memristive probabilistic adder provides a different approach from the typical approximate CMOS adders. Furthermore, it allows for a high area saving and design exibility between the performance and power saving. To reach a similar performance level as approximate CMOS adders, the memristive adder achieves 60% of power saving. An image-compression application is investigated using the memristive probabilistic adders with the performance and the energy trade-off.

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Quality inspection is an indispensable part of the production process of screws for hardware manufactories. In general, hardware manufactories do the quality test of screws by using an electric screwdriver to twist screws. However, there are some limitations and shortcomings in the manual inspection. Firstly, the efficiency of manual inspection is low. Second, manual inspection is difficult to achieve continuous working for 24 hours, which will make a high wage cost. In this thesis, in order to enhance the inspection efficiency and save test costs, we propose to use the image recognition technology of memristor neural networks to check the quality of screws. Here, we discuss different training models of neural networks, namely: convolutional neural networks, one-layer memristor neural network with fixed learning rates. By using the dataset of 8,202 screw head images, experimental results show that the classification accuracy of CNNs and memristor neural networks can achieve 96% and 90%, respectively, which prove the effectiveness of the proposed method.

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Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory and computation units. The computation of Boolean formulas using memristor circuits has been a subject of several recent investigations. Crossbar computing, in general, has also been a topic of active interest, but sneak paths have posed a hurdle in the design of pervasive general-purpose crossbar computing paradigms. In this paper, we demonstrate that sneak paths in nano-crossbar computing can be exploited to design a Boolean-formula evaluation strategy. We demonstrate our approach on a simple Boolean formula and a 1-bit addition circuit. We also conjecture that our nano-crossbar design will be an effective approach for synthesizing high-performance customized arithmetic and logic circuits.

Yes / Fractional-order chaotic systems have more complex dynamics than integer-order chaotic systems. Thus, investigating fractional chaotic systems for the creation of image cryptosystems has been popular recently. In this article, a fractional-order memristor has been developed, tested, numerically analyzed, electronically realized, and digitally implemented. Consequently, a novel simple three-dimensional (3D) fractional-order memristive chaotic system with a single unstable equilibrium point is proposed based on this memristor. This fractional-order memristor is connected in parallel with a parallel capacitor and inductor for constructing the novel fractional-order memristive chaotic system. The system’s nonlinear dynamic characteristics have been studied both analytically and numerically. To demonstrate the chaos behavior in this new system, various methods such as equilibrium points, phase portraits of chaotic attractor, bifurcation diagrams, and Lyapunov exponent are investigated. Furthermore, the proposed fractional-order memristive chaotic system was implemented using a microcontroller (Arduino Due) to demonstrate its digital applicability in real-world applications. Then, in the application field of these systems, based on the chaotic behavior of the memristive model, an encryption approach is applied for grayscale original image encryption. To increase the encryption algorithm pirate anti-attack robustness, every pixel value is included in the secret key. The state variable’s initial conditions, the parameters, and the fractional-order derivative values of the memristive chaotic system are used for contracting the keyspace of that applied cryptosystem. In order to prove the security strength of the employed encryption approach, the cryptanalysis metric tests are shown in detail through histogram analysis, keyspace analysis, key sensitivity, correlation coefficients, entropy analysis, time efficiency analysis, and comparisons with the same fieldwork. Finally, images with different sizes have been encrypted and decrypted, in order to verify the capability of the employed encryption approach for encrypting different sizes of images. The common cryptanalysis metrics values are obtained as keyspace = 2648, NPCR = 0.99866, UACI = 0.49963, H(s) = 7.9993, and time efficiency = 0.3 s. The obtained numerical simulation results and the security metrics investigations demonstrate the accuracy, high-level security, and time efficiency of the used cryptosystem which exhibits high robustness against different types of pirate attacks.

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Les architectures d’ordinateur classiques sont optimisées pour le traitement déterministe d’informations pré-formatées et ont donc des difficultés avec des données naturelles bruitées (images, sons, etc.). Comme celles-ci deviennent nombreuses, de nouveaux circuits neuromorphiques (inspirés par le cerveau) tels que les réseaux de neurones émergent. Des nano-dispositifs, appelés memristors, pourraient permettre leur implémentation sur puce avec une haute efficacité énergétique et en s’approchant de la haute connectivité synaptique du cerveau.Dans ce travail, nous étudions des memristors basés sur des jonctions tunnel ferroélectriques qui sont composées d’une couche ferroélectrique ultramince entre deux électrodes métalliques. Nous montrons que le renversement de la polarisation de BiFeO3 induit des changements de résistance de quatre ordres de grandeurs et établissons un lien direct entre les états de domaines mixtes et les niveaux de résistance intermédiaires.En alternant les matériaux des électrodes, nous révélons leur influence sur la barrière électrostatique et les propriétés dynamiques des memristors. Des expériences d’impulsion unique de tension montrent un retournement de polarisation ultra-rapide. Nous approfondissons l’étude de cette dynamique par des mesures d’impulsions cumulées. La combinaison de leur analyse avec de l’imagerie par microscopie à force piézoélectrique nous permet d’établir un modèle dynamique du memristor. Suite à la démonstration de la spike-timing-dependent plasticity, une règle d’apprentissage importante, nous pouvons prédire le comportement de notre synapse artificielle. Ceci représente une avance majeure vers la réalisation de réseaux de neurones sur puce dotés d’un auto-apprentissage non-supervisé. / Classical computer architectures are optimized to process pre-formatted information in a deterministic way and therefore struggle to treat unorganized natural data (images, sounds, etc.). As these become more and more important, the brain inspires new, neuromorphic computer circuits such as neural networks. Their energy-efficient hardware implementations will greatly benefit from nanodevices, called memristors, whose small size could enable the high synaptic connectivity degree observed in the brain.In this work, we concentrate on memristors based on ferroelectric tunnel junctions that are composed of an ultrathin ferroelectric film between two metallic electrodes. We show that the polarization reversal in BiFeO3 films can induce resistance contrasts as high as 10^4 and how mixed domain states are connected to intermediate resistance levels.Changing the electrode materials provides insights into their influence on the electrostatic barrier and dynamic properties of these memristors. Single-shot switching experiments reveal very fast polarization switching which we further investigate in cumulative measurements. Their analysis in combination with piezoresponse force microscopy finally allows us to establish a model describing the memristor dynamics under arbitrary voltage signals. After the demonstration of an important learning rule for neural networks, called spike-timing-dependent plasticity, we successfully predict new, previously unexplored learning curves. This constitutes an important step towards the realization of unsupervised self-learning hardware neural networks.

Dans le contexte actuel des technologies de l’information, le traitement séquentiel effectué par les ordinateurs d’architecture classique bute sur des problématiques de consommation d’énergie. En s’inspirant de la nature, et tout particulièrement du cerveau, une solution alternative apparaît à travers les réseaux de neurones artificiels. Dans ce cadre, la réalisation de nano-composants, appelés memristors, qui miment la plasticité synaptique, permet grâce à leur taille nanométrique d’envisager la réalisation de réseaux neuronaux densément interconnectés. Dans ce travail de thèse, notre intérêt est porté sur la réalisation d’un tel composant, défini comme une nano-résistance variable et non-volatile, et dont le fonctionnement repose sur le principe de la spintronique (ou l’utilisation du spin des électrons comme vecteur d’information), qui présente les avantages de compatibilité avec les technologies actuelles (CMOS, MRAM, …etc). En utilisant une jonction tunnel magnétique, le concept de memristor spintronique repose sur le déplacement d’une paroi de domaine magnétique par transfert de spin, où chaque position de paroi défini un état de résistance intermédiaire. Afin de maitriser les variations de résistance du dispositif memristif spintronique, l’étude des propriétés statiques et dynamiques de la paroi de domaine sous l’influence d’un courant polarisé en spin est requise. Grâce à l’étude du déplacement et de la résonance de la paroi dans des systèmes à aimantations planaires, comprenant un nombre limité de 3 états intermédiaires de résistance, nous avons pu établir un premier bilan (temps de commutation du dispositif inférieur à la nanoseconde et mis en avant d’un phénomène de ‘sur-amortissement’). En s’appuyant sur ces travaux préliminaires, nous avons par la suite optimisé des jonctions tunnel magnétiques à aimantations perpendiculaires, pour lesquels d’une part le nombre d’états intermédiaires de résistance se voit fortement augmenter (entre 15 et 20 états), autorisant l’utilisation de ce dispositif memristif spintronique pour la réalisation de tâches neuromorphiques. D’autre part, ce dispositif est optimisé pour exploiter le couple de transfert de spin le plus efficace afin de déplacer la paroi de domaine. / In the current context of information technology, the sequential processing carried out by classical computer architectures stumbles on problems of energy consumption. Inspired by nature, especially the brain, an alternative solution appears through artificial neural networks. In this background, the realization of nano-components, called memristors, which mimic synaptic plasticity, enables to consider achieving densely interconnected neural networks due to their small size. In this work, our focus is on the realization of such a component, defined as a tunable and non-volatile nano-resistor, and which operation is based on the principle of spintronics (use of the spin of electrons as information vector), which has the advantages of compatibility with current technologies (CMOS, MRAM …etc). By using a magnetic tunnel junction, the concept of the spintronic memristor is based on the motion of a magnetic domain wall by spin transfer effect, where each wall position defines an intermediate resistance state. In order to control the resistance of this spintronic memristive device, the study of static and dynamic properties of the domain wall under the influence of a spin polarized current is required. By the study of the displacement and resonance of the wall whithin an in-plane magnetized device, we established a first assessment (commutation time of the device below one nanosecond and observation of an over-damping). Based on these preliminary studies, we then optimized magnetic tunnel junctions with out-of-plane magnetizations. On one hand, we show that the number of intermediate resistance states is strongly increased (between 15 and 20 states), allowing this spintronic memristive device to be used to perform neuromorphic tasks. Furthermore, we show that the device is optimized to use the most efficient spin transfer torque to displace the magnetic domain wall.