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AN ABSTRACT OF THE THESIS OFAPARNA REDDY KOTTE, for the Master of science degree in Electrical and Computer Engineering, presented on November 5,2020, at Southern Illinois University Carbondale. TITLE: MEMRISTOR BASED SRAM MAJOR PROFESSOR: Dr. Haniotokis Themistoklis The easy usage and less standby leakage are the main reasons SRAMs are mostly used for mobile applications both on chip and off chip memories. Various SRAM cells have been under research for many years. In post-CMOS era, rising of memristor technology is expected to be a key driver due to its outstanding features to replace the present memory technologies. Memristor is a non-volatile component that memorizes the proportion of current passed through it, reserving the data in the form of resistance. With its non-volatile characteristics, ultra-low power consumption, higher density capability, fast operating speed, ability to function as a multi-level cell and good scalability and compatibility with CMOS technology, memristor technology is found to be best to replace the SRAM cells. Memristor based SRAM cell can be an efficient circuit component that is being proposed in this thesis which consumes less power and allows the conventional SRAM cell to retain data with lesser number of transistors at power-down without any auxiliary circuit. This thesis contains the operating procedure and simulated results of the proposed four transistor and two memristor SRAM using 90nm technology performed on Cadence Virtuoso tool.

<p> Early detection of pathogens in food and water samples is essential in containing and preventing the spread of various diseases, such as campylobacter jejuni or E-coli. In the food processing industry, fast and reliable methods for testing products against contamination would mean faster delivery and better food quality. The pairing specificity of complementary DNA strands provides a highly selective means of detecting pathogens based on their genomic content. Recently, a lot of research has been directed towards the use of mainstream semiconductor technology to build highly sensitive and cheap DNA hybridization sensors. Typically, the gate of a metal-oxide-semiconductor (MOS) transistor is removed, and probe single-stranded DNA molecules are added to the exposed insulator. Complementary DNA hybridization from a solution sample can then be sensed electrostatically by the underlying Field-Effect transistor (FET). </p> <p> The work in this thesis is concerned with the mathematical modeling of FET based biosensors, named BioFETs. Modeling will enable the assessment of the sensitivity of such devices, as well as the potential for using the BioFETs in creating fully electronic microarrays. The mathematical model presented here captures the effects of ionic charge screening of the DNA charges by counterions in the ambient solution, and the effects of surface adsorption that can also aid in the charge screening process. The effects of varying different parameters on the sensitivity of the BioFET are investigated, and the noise contributed by the FET structure is incorporated into the analysis to quantify the expected signal-to-noise ratio (SNR) ofthe BioFET. </p> <p> In order to gain further insight into the operation of the BioFET, linear approximations are applied to the different regions of the BioFET to arrive at an analytic expression that approximates its expected response to DNA hybridization. The approximations are verified by comparing them against the results obtained from the physical model. Finally, different circuit configurations are presented that allow for highly sensitive biosensors to be realized using the BioFET, and a description of a fabricated electronic DNA microarray chip in standard CMOS 0.8 μm is presented. </p> / Thesis / Master of Applied Science (MASc)

Dans la réalisation de circuits intégrés hybrides électroniques - photoniques pour les réseaux télécom, les modulateurs intégrés plasmoniques pourront jouer un role essentiel de codage de l'information en signaux optiques. Cette thése montre la réalisation d'une approche modulateur plasmonique a effet de champ, intégrée en silicium en utilisant les technologies CMOS standards. Ce modulateur MOS plasmonique présente diverses propriétés intéressantes, a savoir un confinement optique fort, permettant une augmentation de l'interaction lumiére matiére. Ces modulateurs plasmoniques permettent aussi de réduire l'inadéquation entre la taille des dispositifs en photonique Si et celle de l' électronique, ce qui permet d'envisager une convergence de leur fabrication en technologie VLSI sur une meme puce. Le modulateur étudié dans ce mémoire repose sur l'accumulation de porteurs dans un condensateur MOS a grille cuivre integer dans un guide d'onde en silicium, nécessitant aux technologies front end et back end Cu d etre combinés de quelques nanométres l'une de l'autre. Nous présentons aussi de nouveaux designs pour injecter de la lumiére a partir de guide d'onde SOI dans un guide a nanostructure plasmonique et les mesures d'une modulation électro-optique dans les structures MOS plasmoniques / Compact and low energy consumption integrated optical modulator is urgently required for encoding information into optical signals. To that respect, the use of plasmon modes to modulate light is of particular interest when compared to the numerous references describing silicon based optical modulators. Indeed, the high field confinement properties of those modes and the increased sensitivity to small refractive index changes of the dielectric close to the metal can help decrease the characteristic length scales of the devices, towards to that of microelectronics.This thesis investigates the realization of Si field-effect plasmonic modulator integrated with a silicon-on insulator waveguide (SOI-WG) using the standard CMOS technology. The material aspects and also the technological steps required in order to realize an integrated plasmonic modulator compatible with requirements of CMOS technology were investigated. First, we demonstrate a Metal-Nitride-Oxide-Semiconductor (MNOS) stack for applications in electro-optical plasmonic devices, so that a very low optical losses and reliable operation is achieved. This objective is met thanks to a careful choice of materials: (i) copper as a metal for supporting the plasmonic mode and (ii) stoechiometric silicon nitride as an ultrathin low optical loss diffusion barrier to the copper. Final electrical reliability is above 95% for a 3 nm thick Si3N4 layer, leakage current density below 10-8 A.cm-2 and optical losses as low as 0.4 dB.μm-1 for a 13 nm thick insulator barrier, in agreement with the losses of the fundamental plasmonic mode estimated by 3D FDTD calculations, using the optical constant of Cu measured from ellipsometry. After demonstrating the MNOS as an appropriate structure for electro-optical CMOS plasmonics, we fabricate a vertical Metal-Insulator-Si-Metal (MISM) waveguide integrated with an SOI-WG, where the back metal was fabricated by flipping and molecular bonding of the original SOI wafer on a Si carrier wafer. The active device area varies from 0.5 to 3 μm2, 0.5 μm width and length varying from 1 to 6 μm.An efficient and simple way to couple light from Si-WG to vertical MISM PWG was experimentally realized by inserting a Metal-Insulator-Si-Insulator (MISI) coupling section between the two waveguides. We demonstrate that such couplers operates at 1.55 μm with the highest efficiency geometry corresponds to a compact length of 0.5 μm with coupling loss of just 2.5 dB (50 %) per facets. This value is 3 times smaller compared to the case of direct coupling (without any MISI section). High-k dielectrics are demonstrated as promising solution to reduce both the MISM absorption loss and the operation voltage. Given that interest, we experimental demonstrate an electrical reliable high-k stack for future applications to the MOS plasmonic modulators.A few μm long plasmonic modulator is experimentally investigated. Devices show leakage current below 10 fA through the copper electrodes based MOS capacitance. The accumulation capacitance (few fF) was found to scale with the surface of the device, in consistent with the expected equivalent oxide thickness of the MOS stack of our modulator. A low electro-absorption (EA) modulation showing capacitive behaviour was experimentally demonstrated in agreement with simulations. Finally, low energy consumption devices 6 fJ per bit was demonstrated.

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No intervalo de valores de frequência de poucos kHz até 1 MHz, nomeado às vezes como região de dispersão ?, as estruturas das células são o principal determinante da impedância do tecido. Esse é o fundamento básico da Espectroscopia da Bioimpedância Elétrica - EBE, a qual tem importância significativa como ferramenta de diagnóstico do câncer de colo no útero - CCU. A EBE consiste na medição de impedância elétrica do tecido cervical para diferentes valores de frequência. A diferença do comportamento no valor da impedância na frequência entre o tecido normal e o cancerígeno é usada para detectar o nível de neoplasia. Um bloco importante do Sistema EBE é o bloco gerador de sinal, o qual está composto principalmente de: a) Oscilador Controlado Numericamente - NCO, b) Conversor Digital - Analógico - DAC e c) Fonte de Corrente Controlada por Tensão - VCCS. O Objetivo do presente trabalho foi o projeto dos blocos principais do Gerador de Sinal para aplicação da Espectroscopia da Bioimpedância Elétrica na Detecção do Câncer no colo do Útero. O Gerador de Sinal é composto de: Oscilador Controlado Numericamente baseado no algoritmo de CORDIC, Conversor Digital - Analógico de 10 bits e Fonte de Corrente Controlada por Tensão. É apresentado o projeto do Oscilador Controlado Numericamente (NCO) de 10 bits baseado na arquitetura iterativa do CORDIC e otimizado em termos da área. O NCO foi implementado na Tecnologia CMOS do Processo da TSMC 180 nm por meio do FREE MINI@SIC IMEC-TSMC 2015. As especificações do projeto foram obtidas dos requerimentos da aplicação da Espectroscopia da Bioimpedância Elétrica - EBE na detecção do Câncer no Colo do Útero - CCU. A arquitetura proposta é composta fundamentalmente de: seletor de frequência de 5 bits, gerador do valor angular, bloco de pré-rotação, unidade aritmética do CORDIC, Unidade de Controle e tabela de busca da referência para arco-tangente. A área do núcleo para este componente foi de 133µmx133µm, ou seja, 0,017689 mm². Foi configurado para gerar 32 valores de frequência de sinais sinusoidais no intervalo de valores de frequência de 100 Hz até 1 MHz com um erro máximo de 0,00623% entre os valores de frequência obtidos da simulação e os resultados experimentais. O Conversor Digital - Analógico foi projetado no nível do esquemático numa arquitetura Current-Steering Segmentada 6-4 com valores de DNL<0,1 LSB e INL<0,2 LSB obtidos na análise de corners. O circuito VCCS foi projetado, simulado e fabricado em Tecnologia CMOS da TSMC 130 nm com polarização de 1,3 V. A Fonte de Corrente de Howland proposta foi baseada no amplificador operacional auto polarizado complementar de cascode dobrado (SB-CFC). De acordo com os requerimentos do padrão internacional IEC:60601-1 o valor pico da corrente sinusoidal foi ajustado em 10 µA. De acordo com aplicação da EBE para a CCD, as especificações do SB-CFC-AO foram calculadas para obter uma corrente sinusoidal na faixa de frequência de 100 Hz até 1 MHz com impedância de saída maior do que 1 MOhm a 1 MHz de frequência. Foram executadas simulações post-layout e os principais resultados foram: 10±0,0035 µA para a amplitude na corrente de saída na faixa de frequência especificada com 5 kOhm de resistência de carga, valores de impedância de saída maiores do 1,6 MOhm a 1 MHz; variações na amplitude da corrente de saída menores do que 0,4% para impedância de carga de 10 Ohm até 5 kOhm. O resultado experimental em termos de não-linearidade apresentou o máximo de 2% da plena escala. De acordo com os resultados obtidos, o desempenho do VCCS é adequado para aplicações da EBE na CCD. / In the frequency range of a few kHz to 1 MHz, sometimes referred to as the ? dispersion region, cell structures are the main determinant of tissue impedance. That is a basic fundamental of Electrical Bio-Impedance Spectroscopy - EBS, which has a significant importance as a diagnostic tool for Cervical Cancer Detection - CCD. EBS consists in the measurements of Electrical Impedance of cervical tissue at different values of frequency. The difference of behavior of impedance value in the frequency of normal tissue and cancerous tissue is used to detect the level of neoplasia. An important block of EBS System is the block signal generator, which is mainly composed of: a) Numerically Controlled Oscillator - NCO, b) Digital to Analog Converter - DAC and c) Voltage Controlled Current Source - VCCS. The aims of this work was to design the main blocks of a Signal Generator for Electrical Bio-Impedance Spectroscopy applied to Cervical Cancer Detection. The signal generator is composed by: CORDIC-Based Numerically Controlled Oscillator, 10-bits Digital-to-Analog Converter and Voltage Controlled Current Source - VCCS. A 10-bit Numerically Controlled Oscillator (NCO) based on the iterative architecture of COordinate Rotation DIgital Computer (CORDIC) optimized in terms of area is presented. The NCO was implemented in a TSMC CMOS 180 nm technology process on the FREE MINI@SIC IMEC-TSMC. The design specifications were obtained from the requirements for application of Electrical Bio-Impedance Spectroscopy (EBS) to Cervical Cancer Detection (CCD). The proposed architecture is basically composed by: 5-bit frequency selector, angle generator, pre-rotator block, CORDIC Arithmetic Unit, Control Unit and lookup table for arctangent reference. The area of this IC for the CORE circuit was 133µm X 133µm, i.e. 0,017689 mm². It was configured in order to generate 32 different frequencies for output sinusoidal signals in the frequency range of 100Hz up to 1MHz with maximum error of 0,00623% in frequency values obtained of comparison of theoretical and experimental results. The 10 bits DAC was implemented in a 6-to-4 Current Steering Segmented architecture with DNL<0,1 LSB and INL<0,2LSB obtained from corners analysis. The circuit VCCS was designed, simulated and fabricated in TSMC 130 nm CMOS technology at 1.3V power supply. The proposed Howland Current Source is based on Self-Biased Complementary Folded Cascode (SB-CFC) Operational Amplifier (OA). Complying with the requirements for medical electrical equipment of international standard ABNT-NBR-IEC-60601-1 the sinusoidal current peak amplitude was settled at 10 µA. In accordance with the requirements of the EBS for CCD, the specifications for the SB-CFC-OA were calculated to meet the 100 Hz to 1 MHz frequency range for the sinusoidal output current and the output impedance higher than 1 MOhm at 1 MHz frequency. Post-layout simulations were run and the main results were: 10 ± 0.0335 µA for the output current peak amplitude over the specified frequency range and with 5 kOhm load impedance; values above 1.6 MOhm output impedance @ 1 MHz; nominal current amplitude variations lower than 0.4% for load impedances in the range of 10 Ohm up to 5 kOhm. And the experimental result for maximum non-linearity was 2% of full scale. From these results, the performance of the VCCS is adequate for EBS-CCD applications.

This thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is also presented. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. A discussion of the different methods of bandwidth extension using inductive peaking is included, and the optimal configurations for maximally flat responses are shown for shunt inductive peaking,series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology is optimized using a novel noise analysis that uses a high frequency noise model for the transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-07-16 13:34:41.46

This thesis presents the design and analysis of two high speed analog laser driver stages (LDS) for use in a passive optical network (PON) upstream burst-mode transmitter (BM-Tx) using low cost complementary metal oxide semiconductors (CMOS) technology. The maturation of CMOS technology has lead to aggressive scaling of device sizes which has made it an increasingly attractive technology for high speed analog design. CMOS provides high levels of integration as it is the industry standard for digital circuits, analog and digital systems can share one substrate reducing costs. Additionally CMOS is a more cost effective solution than traditional expensive high speed analog substrates. A 2.5 Gbps LDS fabricated in 0.18 um CMOS technology is presented. The LDS uses a two stage per-amplifier. Stage one consists of a cascode differential pair with a source follower voltage buffer, while stage two consists of a shunt inductively peaked differential pair using active inductors. A differential pair composed of large transistors is used in an open drain configuration for the output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 14.6-58 mA. 10%-90% approximate rise/fall times of 230/260 ps was obtained for a modulation current of 58 mA. Power consumption of the core was determined to be 68.5 mW, while the chip consumed an area of 0.8 mm x 0.7 mm including pads. A 10 Gbps LDS fabricated in 0.18 um CMOS technology is also presented. The LDS uses a cascode differential pair for the output stage. The per-amplifier for this design consists of a differential pair and utilizes spiral inductors for series inductive peaking between the per-amplifier and output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 22.6-62 mA. 10%-90% rise/fall time of 87 ps and 75 ps are respectively obtained while operating at maximum modulation current. The core of the LDS consumes a power of 287 mW, while the chip consumed an area of 0.79 mm x 0.7mm. The measured electrical eye diagrams for the 2.5 Gbps and the 10 Gbps meet the timing requirements for the GPON standard. Further work is needed to investigate whether or not the timing requirements would still be met once the CMOS chips are integrated with commercial laser diodes. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-09-24 10:43:33.418

Recent trends in mobile broadband indicates that the available radio frequency (RF) spectrum will not be enough to support the data requirements of the immediate future. Visible light communication, which uses visible spectrum to transmit wirelessly could be a potential solution to the RF ’Spectrum Crunch’. Thus there is growing interest all over the world in this domain with support from both academia and industry. Visible light communication( VLC) systems make use of light emitting diodes (LEDs), which are semiconductor light sources to transmit information. A number of demonstrators at different data capacity and link distances has been reported in this area. One of the key problems holding this technology from taking off is the unavailability of power efficient, miniature LED drive schemes. Reported demonstrators, mostly using either off the shelf components or arbitrary waveform generators (AWGs) to drive the LEDs have only started to address this problem by adopting integrated drivers designed for driving lighting installations for communications. The voltage regulator based drive schemes provide high power efficiency (> 90 %) but it is difficult to realise the fast switching required to achieve the Mbps or Gbps data rates needed for modern wireless communication devices. In this work, we are exploiting CMOS technology to realise an integrated LED driver for VLC. Instead of using conventional drive schemes (digital to analogue converter (DAC) + power amplifier or voltage regulators), we realised a current steering DAC based LED driver operating at high currents and sampling rates whilst maintaining power efficiency. Compared to a commercial AWG or discrete LED driver, circuit realised utilisng complementary metal oxide semiconductor (CMOS) technology has resulted in area reduction (29mm2). We realised for the first time a multi-channel CMOS LED driver capable of operating up to a 500 MHz sample rate at an output current of 255 mA per channel and > 70% power efficiency. We were able to demonstrate the flexibility of the driver by employing it to realise VLC links using micro LEDs and commercial LEDs. Data rates up to 1 Gbps were achieved using this system employing a multiple input, multiple output (MIMO) scheme. We also demonstrated the wavelength division multiplexing ability of the driver using a red/green/blue commercial LED. The first integrated digital to light converter (DLC), where depending on the input code, a proportional number of LEDs are turned ON, realising a data converter in the optical domain, is also an output from this research. In addition, we propose a differential optical drive scheme where two output branches of a current DAC are used to drive two LEDs achieving higher link performance and power efficiency compared to single LED drive.