This thesis focuses on design of an accurate digital to analog converter (DAC). The thesis provides material to understand the principle of conversion of digital signal to analog signal. Some possible structures of DAC are described in this thesis. The selected structure is used for design of the DAC using the CMOS 07 technology. Functionality of the DAC is verified with simulations using the PSPICE simulation program.

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Fluorescence based analysis is a fundamental research technique used in the life sciences. However, conventional fluorescence intensity measurements are prone to misinterpretation due to illumination and fluorophore concentration non-uniformities. Thus, there is a growing interest in time-resolved fluorescence detection, whereby the characteristic fluorescence decay time-constant (or lifetime) in response to an impulse excitation source is measured. The sensitivity of a sample’s lifetime properties to the micro-environment provides an extremely powerful analysis tool. However, current fluorescence lifetime analysis equipment tends to be bulky, delicate and expensive, thereby restricting its use to research laboratories. Progress in miniaturisation of biological and chemical analysis instrumentation is creating low-cost, robust and portable diagnostic tools capable of high-throughput, with reduced reagent quantities and analysis times. Such devices will enable point-of-care or in-the-field diagnostics. It was the ultimate aim of this project to produce an integrated fluorescence lifetime analysis system capable of sub-nano second precision with an instrument measuring less than 1cm3, something hitherto impossible with existing approaches. To accomplish this, advances in the development of AlInGaN micro-LEDs and high sensitivity CMOS detectors have been exploited. CMOS allows electronic circuitry to be integrated alongside the photodetectors and LED drivers to produce a highly integrated system capable of processing detector data directly without the need for additional external hardware. In this work, a 16x4 array of single-photon avalanche diodes (SPADs) integrated in a 0.35μm high-voltage CMOS technology has been implemented which incorporates two 9-bit, in-pixel time-gated counter circuits, with a resolution of 400ps and on-chip timing generation, in order to directly process fluorescence decay data. The SPAD detector can accurately capture fluorescence lifetime data for samples with concentrations down to 10nM, demonstrated using colloidal quantum dot and conventional fluorophores. The lifetimes captured using the on-chip time gated counters are shown to be equivalent to those processed using commercially available external time-correlated single-photon counting (TCSPC) hardware. A compact excitation source, capable of producing sub-nano second optical pulses, was designed using AlInGaN micro-LEDs bump-bonded to a CMOS driver backplane. A series of driver array designs are presented which are electrically contacted to an equivalent array of micro-LEDs emitting at a wavelength of 370nm. The final micro-LED driver design is capable of producing optical pulses of 300ps in width (full width half maximum, FWHM) and a maximum DC optical output power of 550μW, this is, to the best of our knowledge, the shortest reported optical pulse from a CMOS driven micro-LED device. By integrating an array of CMOS SPAD detectors and an array of CMOS driven AlInGaN micro-LEDs, a complete micro-system for time-resolved fluorescence analysis has been realised. Two different system configurations are evaluated and the ability of both topologies to accurately capture lifetime data is demonstrated. By making use of standard CMOS foundry technologies, this work opens up the possibility of a low-cost, portable chemical/bio-diagnostic device. These first-generation prototypes described herein demonstrate the first time-resolved fluorescence lifetime analysis using an integrated micro-system approach. A number of possible design improvements have been identified which could significantly enhance future device performance resulting in increased detector and micro-LED array density, improved time-gate resolution, shorter excitation pulse widths with increased optical output power and improved excitation light filtering. The integration of sample handling elements has also been proposed, allowing the sample of interest to be accurately manipulated within the micro-environment during investigation.

L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire dans la diminution de la fiabilité des composants électroniques aussi bien dans l’environnement radiatif spatial que terrestre. Cette étude porte sur la modélisation des mécanismes physiques qui conduisent à ces aléas logiques (en anglais "Soft Errors"). Ces modèles sont utilisés dans une plateforme de simulation,appelée TIARA (Tool suIte for rAdiation Reliability Assessment), qui a été développée dans le cadre de cette thèse. Cet outil est capable de prédire la sensibilité de nombreuses architectures de circuits (SRAM,Flip-Flop, etc.) dans différents environnements radiatifs et sous différentes conditions de test (alimentation, altitude, etc.) Cette plateforme a été amplement validée grâce à la comparaison avec des mesures expérimentales effectuées sur différents circuits de test fabriqués par STMicroelectronics. La plateforme TIARA a ensuite été utilisée pour la conception de circuits durcis aux radiations et a permis de participer à la compréhension des mécanismes des aléas logiques jusqu’au noeud technologique 20nm. / Aggressive integrated circuit density increase and power supply scaling have propelled Single Event Effects to the forefront of reliability concerns in ground-based and space-bound electronic systems. This study focuses on modeling of Single Event physical phenomena. To enable performing reliability assessment, a complete simulation platform named Tool suIte for rAdiation Reliability Assessment (TIARA) has been developed that allows performing sensitivity prediction of different digital circuits (SRAM, Flip-Flops, etc.) in different radiation environments and at different operating conditions (power supply voltage,altitude, etc.) TIARA has been extensively validated with experimental data for space and terrestrial radiation environments using different test vehicles manufactured by STMicroelectronics. Finally, the platform has been used during rad-hard digital circuits design and to provide insights into radiation-induced upset mechanisms down to CMOS 20nm technological node.

Os estados emaranhados da luz são de grande importância para protocolos de comunicação quântica. Uma das principais fontes que vem sendo estudada no Laboratório de Manipulação Coerente de Átomos e Luz - LMCAL é o oscilador paramétrico ótico (OPO) no qual, através de processos paramétricos não lineares de segunda e terceira ordem (x(2) e x(3)), são produzidos feixes intensos que apresentam correlações quânticas. Recentemente, o LMCAL vem explorando o processo de mistura de quatro ondas (fenômeno derivado da susceptibilidade de terceira ordem x(3)) como fonte geradora de feixes emaranhados. Inicialmente, foi realizado a partir de células de rubídio e agora, em colaboração com o grupo de pesquisa da Profa. Michal Lipson da Universidade de Columbia, em chips de nitreto de silício (Si3N4); permitindo assim possibilidades de modulação ultra-rápida, confinamento de luz em volumes muito reduzidos, além da ótica não-linear do OPO. O presente projeto visa estudar as propriedades quânticas da luz nos OPOs em chips de silício, permitindo que sistemas muito eficientes em informação clássica possam ser usados também para implementação de protocolos de informação quântica. / Entangled States of light beams are of great importance for quantum communication protocols. One of the most relevant source of such states which is being studied at the Laboratory of Coherent Manipulation of Atoms and Light - LMCAL (in portuguese) is the Optical Parametric Oscillator (OPO) which through second and third order nonlinear parametric processes (x(2) and x(3)) produces intense fields that have quantum correlations. Recently, LMCAL is exploring four-wave mixing (FWM), a third-order nonlinear parametric process, as a source of entangled beams. Initially, on rubidium cells and now, in collaboration with Prof. Michal Lipson from the Columbia University, on silicon nitride (Si3N4) chips; opening a new avenue for ultrafast modulation, light confinement in reduced light volumes, as well as the nonlinear optics of the OPO. This project is intended to study quantum properties of light of on-chip OPOs in order to achieve the integration of these highly efficient devices for implementations of quantum information protocols.

Les travaux de cette thèse sont axés sur le durcissement à la dose cumulée des circuits analogiques associés aux systèmes électroniques embarqués sur des véhicules spatiaux, satellites ou sondes. Ces types de circuits sont réputés pour être relativement sensibles à la dose cumulée, parfois dès quelques krad, souvent en raison de l’intégration d’éléments bipolaires. Les nouvelles technologies CMOS montrent par leur intégration de plus en plus poussée, un durcissement naturel à cette dose. L’approche de durcissement proposée ici, repose sur un durcissement par la conception d’une technologie commerciale « full CMOS » du fondeur ST Microelectronics, appelée HCMOS9A. Cette approche permet d’assurer la portabilité des méthodes de durcissement proposées d’une technologie à une autre et de rendre ainsi accessible les nouvelles technologies aux systèmes spatiaux. De plus, cette approche de durcissement permet de faire face aux coûts croissants de développement et d’accès aux technologies durcies. Une première technique de durcissement à la dose cumulée est appliquée à une tension de référence « full CMOS ». Elle ne fait intervenir ni jonction p-n parasites ni précautions delay out particulières mais la soustraction de deux tensions de seuil qui annulent leurs effets à la dose cumulée entre elles. Si les technologies commerciales avancées sont de plus en plus utilisées pour des applications spécialement durcies, ces dernières exhibent en contrepartie de plus grands offsets que les technologies bipolaires. Cela peut affecter les performances des systèmes. La seconde technique étudiée : l’auto zéro, est une solution efficace pour réduire les dérives complexes dues entre autres à la température, de l’offset d’entrée des amplificateurs opérationnels. Le but ici est de prouver que cette technique peut tout aussi bien contrebalancer les dérives de l’offset dues à la dose cumulée. / The purpose of this thesis work is to investigate circuit design techniques to improve the robustness to Total Ionizing Dose (TID) of analog circuits within electronic systems embedded in space probes, satellites and vehicles. Such circuits often contain bipolartransistor components which are quite sensitive to cumulated radiation dose. However highly integrated CMOS technology has been shown to exhibit better natural TDI hardening.The approach proposed here is a hardening by design using a full CMOS semiconductor technology commercially available from ST Microelectronics calledHCMOS9A. The proposed generic hardening design methods will be seen to be compatibleand applicable to other existing or future process technologies. Furthermore this approach addresses the issue of ever-increasing development cost and access to hardened technologies.The first TID hardening technique proposed is applied to a full-CMOS voltage reference. This technique does not involve p-n junctions nor any particular layout precaution but instead is based on the subtraction of two different threshold voltages which allows the cancellation of TDI effects. While the use of advanced commercial CMOS technologies for specific radiation hardened applications is becoming more common, these technologies suffer from larger inputoffs et voltage drift than their bipolar transistor counterparts, which can impact system performance. The second technique studied is that of auto-zeroing, which is an efficient method to reduce the complex offset voltage drift mechanisms of operational amplifiers due to temperature. The purpose here is to prove that this technique can also cancel input offset voltage drift due to TID.Index term : hardening, cumulated dose, CMOS technology, voltage reference,operational amplifier.

The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices. First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification. Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability. Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology. / QC20100708 / NEMO, NANOSIL, SINANO

The purpose of this thesis is to design a secure and optimized cryptographic stream cipher for passive type Radio Frequency Identification (RFID) tags. RFID technology is a wireless automatic tracking and identification device. It has become an integral part of our daily life and it is used in many applications such as electronic passports, contactless payment systems, supply chain management and so on. But the information carried on RFID tags are vulnerable to unauthorized access (or various threats) which raises the security and privacy concern over RFID devices. One of the possible solutions to protect the confidentiality, integrity and to provide authentication is, to use a cryptographic stream cipher which encrypts the original information with a pseudo-random bit sequence. Besides that RFID tags require a resource constrained environment such as efficient area, power and high performance cryptographic systems with large security margins. Therefore, the architecture of stream cipher provides the best trade-off between the cryptographic security and the hardware efficiency. In this thesis, we first described the RFID technology and explain the design requirements for passive type RFID tags. The hardware design for passive tags is more challenging due to its stringent requirements like power consumption and the silicon area. We presented different design measures and some of the optimization techniques required to achieve low-resource cryptographic hardware implementation for passive tags. Secondly, we propose and implement a lightweight WG-5 stream cipher, which has good proven cryptographic mathematical properties. Based on these properties we measured the security analysis of WG-5 and showed that the WG-5 is immune to different types of attacks such as algebraic attack, correlation attack, cube attack, differential attack, Discrete Fourier Transform attack (DFT), Time-Memory-Data trade-off attack. The implementation of WG-5 was carried out using 65 nm and 130 nm CMOS technologies. We achieved promising results of WG-5 implementation in terms of area, power, speed and optimality. Our results outperforms most of the other stream ciphers which are selected in eSTREAM project. Finally, we proposed RFID mutual authentication protocol based on WG-5. The security and privacy analysis of the proposed protocol showed that it is resistant to various RFID attacks such as replay attacks, Denial-of-service (DoS) attack, ensures forward privacy and impersonation attack.

The purpose of this thesis is to design a secure and optimized cryptographic stream cipher for passive type Radio Frequency Identification (RFID) tags. RFID technology is a wireless automatic tracking and identification device. It has become an integral part of our daily life and it is used in many applications such as electronic passports, contactless payment systems, supply chain management and so on. But the information carried on RFID tags are vulnerable to unauthorized access (or various threats) which raises the security and privacy concern over RFID devices. One of the possible solutions to protect the confidentiality, integrity and to provide authentication is, to use a cryptographic stream cipher which encrypts the original information with a pseudo-random bit sequence. Besides that RFID tags require a resource constrained environment such as efficient area, power and high performance cryptographic systems with large security margins. Therefore, the architecture of stream cipher provides the best trade-off between the cryptographic security and the hardware efficiency. In this thesis, we first described the RFID technology and explain the design requirements for passive type RFID tags. The hardware design for passive tags is more challenging due to its stringent requirements like power consumption and the silicon area. We presented different design measures and some of the optimization techniques required to achieve low-resource cryptographic hardware implementation for passive tags. Secondly, we propose and implement a lightweight WG-5 stream cipher, which has good proven cryptographic mathematical properties. Based on these properties we measured the security analysis of WG-5 and showed that the WG-5 is immune to different types of attacks such as algebraic attack, correlation attack, cube attack, differential attack, Discrete Fourier Transform attack (DFT), Time-Memory-Data trade-off attack. The implementation of WG-5 was carried out using 65 nm and 130 nm CMOS technologies. We achieved promising results of WG-5 implementation in terms of area, power, speed and optimality. Our results outperforms most of the other stream ciphers which are selected in eSTREAM project. Finally, we proposed RFID mutual authentication protocol based on WG-5. The security and privacy analysis of the proposed protocol showed that it is resistant to various RFID attacks such as replay attacks, Denial-of-service (DoS) attack, ensures forward privacy and impersonation attack.