L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire dans la diminution de la fiabilité des composants électroniques aussi bien dans l’environnement radiatif spatial que terrestre. Cette étude porte sur la modélisation des mécanismes physiques qui conduisent à ces aléas logiques (en anglais "Soft Errors"). Ces modèles sont utilisés dans une plateforme de simulation,appelée TIARA (Tool suIte for rAdiation Reliability Assessment), qui a été développée dans le cadre de cette thèse. Cet outil est capable de prédire la sensibilité de nombreuses architectures de circuits (SRAM,Flip-Flop, etc.) dans différents environnements radiatifs et sous différentes conditions de test (alimentation, altitude, etc.) Cette plateforme a été amplement validée grâce à la comparaison avec des mesures expérimentales effectuées sur différents circuits de test fabriqués par STMicroelectronics. La plateforme TIARA a ensuite été utilisée pour la conception de circuits durcis aux radiations et a permis de participer à la compréhension des mécanismes des aléas logiques jusqu’au noeud technologique 20nm. / Aggressive integrated circuit density increase and power supply scaling have propelled Single Event Effects to the forefront of reliability concerns in ground-based and space-bound electronic systems. This study focuses on modeling of Single Event physical phenomena. To enable performing reliability assessment, a complete simulation platform named Tool suIte for rAdiation Reliability Assessment (TIARA) has been developed that allows performing sensitivity prediction of different digital circuits (SRAM, Flip-Flops, etc.) in different radiation environments and at different operating conditions (power supply voltage,altitude, etc.) TIARA has been extensively validated with experimental data for space and terrestrial radiation environments using different test vehicles manufactured by STMicroelectronics. Finally, the platform has been used during rad-hard digital circuits design and to provide insights into radiation-induced upset mechanisms down to CMOS 20nm technological node.

Field-effect transistor technologies have been critical building blocks for satellite systems since their introduction into the microelectronics industry. The extremely high cost of launching payloads into orbit necessitates systems to have small form factor, ultra low-power consumption, and reliable lifetime operation, while satisfying the performance requirements of a given application. Silicon-based complementary metal-oxide-semiconductors (Si CMOS) have traditionally been able to adequately meet these demands when coupled with radiation hardening techniques that have been developed over years of invested research. However, as customer demands increase, pushing the limits of system throughput, noise, and speed, alternative technologies must be employed. Silicon-germanium BiCMOS platforms have been identfied as a technology candidate for meeting the performance criteria of these pioneering satellite systems and deep space applications, contingent on their ability to be hardened to radiation-induced damage. Given that SiGe technology is a relative new- comer to terrestrial and extra-terrestrial applications in radiation-rich environments, the same wealth of knowledge of time-tested radiation hardening methodologies has not been established as it has for Si CMOS. Although SiGe BiCMOS technology has been experimentally proven to be inherently tolerant to total-ionizing dose damage mechanism, the single event susceptibility of this technology remains a primary concern. The objective of this research is to characterize the physical mechanisms that drive the origination of ion-induced transient terminal currents in SiGe HBTs that subsequently lead to a wide range of possible single event phenomena. Building upon this learning, a variety of device-level hardening methodologies are explored and tested for efficacy.

The aim with this thesis has been to make a survey of radiation hardened electronics, explaining why and how radiation affects electronics and what can be done to harden it. The effects radiation have on electronics in general and in specific commonly used devices are explained qualitatively. The effects are divided into Displacement Damage (DD), Total Ionizing Dose (TID) and Single Event Effects (SEEs). The devices explained are MOSFETs, Silicon On Insulator (SOI) transistors, 3D-transistors, Power transistors, Optocouplers, Field Programmable Gate Arrays (FPGAs), three dimensional circuits (3D-ICs) and Flash memories. Different radiation hardening by design (RHBD) techniques used to reduce or to remove the negative effects radiation induces in electronics are also explained. The techniques are Annular transistors, Enclosed source/drain transistors, Guard rings, Triple Modular Redundancy (TMR), Dual Interlocked Storage Cells (DICE), Guard gates, Temporal filtering,Multiple drive, Charge dissipation, Differential Charge Cancellation (DCC), Scrubbing, Lockstep, EDAC codes and Watchdog timers.

Os efeitos produzidos pela interação da radiação ionizante com os circuitos integrados podem ser classificados em efeitos de eventos únicos (Single Event Effects - SEE), comumente relacionados a problemas transientes, e efeitos de dose total ionizante (Total Ionization Dose - TID), os quais se originam em decorrência do longo tempo de exposição à radiação ionizante. Com relação à proteção desses circuitos, técnicas, como redundâncias temporais e espaciais, podem ser aplicadas a fim de reduzir a ocorrência de eventos transientes. Por outro lado, efeitos de TID e mesmo alguns SEE específicos, como os que causam degradações permanentes do circuito, podem ser atenuados drasticamente através de técnicas propostas em nível de layout. Nesse contexto, este trabalho analisa os conceitos básicos envolvidos na interação da radiação com o transistor MOS, desvios de suas características elétricas e técnicas de atenuação dos efeitos acumulativos aplicadas em níveis de arquitetura de sistemas, de processo de fabricação e de dispositivo. Contudo, este trabalho realiza uma abordagem mais detalhada de técnicas de tolerância em nível de layout. A tolerância em nível de layout do transistor é o resultado da combinação entre tecnologia escolhida agregada ao uso de anéis de guarda (guard rings) e aplicação de técnicas em nível de dispositivo como, por exemplo, a de geometria fechada (enclosed-gate). Este trabalho explora diferentes topologias de geometria fechada analisando diferentes modelagens e estimativas de razão de aspecto (W⁄L). Além disso, todas as análises e propostas apresentadas ao longo deste trabalho levam em conta o ambiente de projeto comercial, de forma que os dispositivos e técnicas propostas possam ser aplicadas e fabricadas utilizando ferramentas de projeto comerciais, respeitando restrições quando a dimensões e espaçamentos entre estruturas de acordo com requisitos comerciais de litografia. Os resultados obtidos corroboram o fato de que ao custo de área é possível que se obtenha um dispositivo mais tolerante à radiação e, neste caso, técnicas de mais alto nível ainda podem ser aplicadas de forma a atingir uma maior eficiência de proteção. / Studies related to ionizing radiation effects into MOS transistors are usually classified into two main groups, Single Event Effects (SEE) and Total Ionization Dose (TID). The former is related to transient effects and the later to the permanent effects which occurs during the whole lifetime of integrated circuits and devices. Architecture level for SEE mitigation techniques usually involves redundancy and majority voters, on the other hand, TID mitigation techniques act avoiding or reducing the weak and critical regions in the layout perspective. In this context this work proposes the analysis of primary physical mechanisms of radiation effects in semiconductor components and MOS transistors by exploring the electrical properties and related degradations. The mitigation (or hardening) techniques are explored not only at the architectural level but also by processes improvements. Nonetheless, this work is primarily focused to achieve a radiation hardened circuit by applying specific changes in the layout perspective making the design named as Radiation Hardened by Design (RHBD). Trading the area and circuit density it is possible to harden the most basic building block of electrical circuits (MOS transistors) and, in this case, by applying higher levels of mitigation techniques it is even possible to harden the entire circuit. Hardening by device is a combination of technology node, use of guard rings and techniques such as Enclosed Layout Transistor (ELT). Thus, this work realizes a comparative study of different proposed models to estimate the effective W/L aspect ratio in ELTs. Moreover, the analysis and approaches presented throughout this work take into account the commercial context, i.e., respecting the commercial Process Design Kits rules.

Os efeitos produzidos pela interação da radiação ionizante com os circuitos integrados podem ser classificados em efeitos de eventos únicos (Single Event Effects - SEE), comumente relacionados a problemas transientes, e efeitos de dose total ionizante (Total Ionization Dose - TID), os quais se originam em decorrência do longo tempo de exposição à radiação ionizante. Com relação à proteção desses circuitos, técnicas, como redundâncias temporais e espaciais, podem ser aplicadas a fim de reduzir a ocorrência de eventos transientes. Por outro lado, efeitos de TID e mesmo alguns SEE específicos, como os que causam degradações permanentes do circuito, podem ser atenuados drasticamente através de técnicas propostas em nível de layout. Nesse contexto, este trabalho analisa os conceitos básicos envolvidos na interação da radiação com o transistor MOS, desvios de suas características elétricas e técnicas de atenuação dos efeitos acumulativos aplicadas em níveis de arquitetura de sistemas, de processo de fabricação e de dispositivo. Contudo, este trabalho realiza uma abordagem mais detalhada de técnicas de tolerância em nível de layout. A tolerância em nível de layout do transistor é o resultado da combinação entre tecnologia escolhida agregada ao uso de anéis de guarda (guard rings) e aplicação de técnicas em nível de dispositivo como, por exemplo, a de geometria fechada (enclosed-gate). Este trabalho explora diferentes topologias de geometria fechada analisando diferentes modelagens e estimativas de razão de aspecto (W⁄L). Além disso, todas as análises e propostas apresentadas ao longo deste trabalho levam em conta o ambiente de projeto comercial, de forma que os dispositivos e técnicas propostas possam ser aplicadas e fabricadas utilizando ferramentas de projeto comerciais, respeitando restrições quando a dimensões e espaçamentos entre estruturas de acordo com requisitos comerciais de litografia. Os resultados obtidos corroboram o fato de que ao custo de área é possível que se obtenha um dispositivo mais tolerante à radiação e, neste caso, técnicas de mais alto nível ainda podem ser aplicadas de forma a atingir uma maior eficiência de proteção. / Studies related to ionizing radiation effects into MOS transistors are usually classified into two main groups, Single Event Effects (SEE) and Total Ionization Dose (TID). The former is related to transient effects and the later to the permanent effects which occurs during the whole lifetime of integrated circuits and devices. Architecture level for SEE mitigation techniques usually involves redundancy and majority voters, on the other hand, TID mitigation techniques act avoiding or reducing the weak and critical regions in the layout perspective. In this context this work proposes the analysis of primary physical mechanisms of radiation effects in semiconductor components and MOS transistors by exploring the electrical properties and related degradations. The mitigation (or hardening) techniques are explored not only at the architectural level but also by processes improvements. Nonetheless, this work is primarily focused to achieve a radiation hardened circuit by applying specific changes in the layout perspective making the design named as Radiation Hardened by Design (RHBD). Trading the area and circuit density it is possible to harden the most basic building block of electrical circuits (MOS transistors) and, in this case, by applying higher levels of mitigation techniques it is even possible to harden the entire circuit. Hardening by device is a combination of technology node, use of guard rings and techniques such as Enclosed Layout Transistor (ELT). Thus, this work realizes a comparative study of different proposed models to estimate the effective W/L aspect ratio in ELTs. Moreover, the analysis and approaches presented throughout this work take into account the commercial context, i.e., respecting the commercial Process Design Kits rules.

Os efeitos produzidos pela interação da radiação ionizante com os circuitos integrados podem ser classificados em efeitos de eventos únicos (Single Event Effects - SEE), comumente relacionados a problemas transientes, e efeitos de dose total ionizante (Total Ionization Dose - TID), os quais se originam em decorrência do longo tempo de exposição à radiação ionizante. Com relação à proteção desses circuitos, técnicas, como redundâncias temporais e espaciais, podem ser aplicadas a fim de reduzir a ocorrência de eventos transientes. Por outro lado, efeitos de TID e mesmo alguns SEE específicos, como os que causam degradações permanentes do circuito, podem ser atenuados drasticamente através de técnicas propostas em nível de layout. Nesse contexto, este trabalho analisa os conceitos básicos envolvidos na interação da radiação com o transistor MOS, desvios de suas características elétricas e técnicas de atenuação dos efeitos acumulativos aplicadas em níveis de arquitetura de sistemas, de processo de fabricação e de dispositivo. Contudo, este trabalho realiza uma abordagem mais detalhada de técnicas de tolerância em nível de layout. A tolerância em nível de layout do transistor é o resultado da combinação entre tecnologia escolhida agregada ao uso de anéis de guarda (guard rings) e aplicação de técnicas em nível de dispositivo como, por exemplo, a de geometria fechada (enclosed-gate). Este trabalho explora diferentes topologias de geometria fechada analisando diferentes modelagens e estimativas de razão de aspecto (W⁄L). Além disso, todas as análises e propostas apresentadas ao longo deste trabalho levam em conta o ambiente de projeto comercial, de forma que os dispositivos e técnicas propostas possam ser aplicadas e fabricadas utilizando ferramentas de projeto comerciais, respeitando restrições quando a dimensões e espaçamentos entre estruturas de acordo com requisitos comerciais de litografia. Os resultados obtidos corroboram o fato de que ao custo de área é possível que se obtenha um dispositivo mais tolerante à radiação e, neste caso, técnicas de mais alto nível ainda podem ser aplicadas de forma a atingir uma maior eficiência de proteção. / Studies related to ionizing radiation effects into MOS transistors are usually classified into two main groups, Single Event Effects (SEE) and Total Ionization Dose (TID). The former is related to transient effects and the later to the permanent effects which occurs during the whole lifetime of integrated circuits and devices. Architecture level for SEE mitigation techniques usually involves redundancy and majority voters, on the other hand, TID mitigation techniques act avoiding or reducing the weak and critical regions in the layout perspective. In this context this work proposes the analysis of primary physical mechanisms of radiation effects in semiconductor components and MOS transistors by exploring the electrical properties and related degradations. The mitigation (or hardening) techniques are explored not only at the architectural level but also by processes improvements. Nonetheless, this work is primarily focused to achieve a radiation hardened circuit by applying specific changes in the layout perspective making the design named as Radiation Hardened by Design (RHBD). Trading the area and circuit density it is possible to harden the most basic building block of electrical circuits (MOS transistors) and, in this case, by applying higher levels of mitigation techniques it is even possible to harden the entire circuit. Hardening by device is a combination of technology node, use of guard rings and techniques such as Enclosed Layout Transistor (ELT). Thus, this work realizes a comparative study of different proposed models to estimate the effective W/L aspect ratio in ELTs. Moreover, the analysis and approaches presented throughout this work take into account the commercial context, i.e., respecting the commercial Process Design Kits rules.

Silicon-germanium (SiGe) BiCMOS technology platforms have proven invaluable for implementing a wide variety of digital, RF, and mixed-signal applications in extreme environments such as space, where maintaining high levels of performance in the presence of low temperatures and background radiation is paramount. This work will focus on the investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform. Tolerance will be quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening will be proposed and tested with the goal of improving the SEE sensitivity of the npn in this platform by reducing the charge collected by the subcollector in the event of a direct ion strike. To the author's knowledge, this work presents the first design and measurement results for this form of RHBD.

Extreme environment applications impose stringent demands on technology platforms that are incorporated in electronic systems. Space is a classic extreme environment, encompassing both large temperature fluctuations as well as intense radiation fields. Silicon-germanium technology has emerged as a competitive platform for space-based applications, owing to its excellent low-temperature performance and total ionizing dose tolerance. This technology has however been repeatedly shown to be vulnerable to single event phenomena induced by galactic cosmic rays as well as trapped particles within the earth's geomagnetic field. To improve the radiation tolerance of systems incorporating SiGe components, modifications to fabrications steps (Radiation Hardening by Process, RHBP) and/or device/circuit topologies (Radiation Hardening by Design, RHBD) may be employed. For this thesis, two methodologies are analyzed, both RHBD techniques which come at no additional power/area penalty for implementation.

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