abstract: Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this thesis. Temporal hardening mitigates both SETs and SEUs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. This thesis presents an innovative, temporally hardened D flip-flop (TFF). The TFF physical design is laid out in the 130 nm TSMC process in the form of an interleaved multi-bit cell and the circuitry necessary for the flip-flop to be hardened against SETs and SEUs is analyzed with simulations verifying these claims. Comparisons are made to an unhardened D flip-flop through speed, size, and power consumption depicting how the RHBD technique used increases all three over an unhardened flip-flop. Finally, the blocks from both the hardened and the unhardened flip-flops being placed in Synthesis and auto-place and route (APR) design flows are compared through size and speed to show the effects of using the high density multi-bit layout. Finally, the TFF presented in this thesis is compared to two other flip-flops, the majority voter temporal/DICE flip-flop (MTDFF) and the C-element temporal/DICE flip-flop (CTDFF). These circuits are built on the same 130 nm TSMC process as the TFF and then analyzed by the same methods through speed, size, and power consumption and compared to the TFF and unhardened flip-flops. Simulations are completed on the MTDFF and CTDFF to show their strengths against D node SETs and SEUs as well as their weakness against CLK node SETs. Results show that the TFF is faster and harder than both the MTDFF and CTDFF. / Dissertation/Thesis / M.S. Electrical Engineering 2010

abstract: Clock generation and distribution are essential to CMOS microchips, providing synchronization to external devices and between internal sequential logic. Clocks in microprocessors are highly vulnerable to single event effects and designing reliable energy efficient clock networks for mission critical applications is a major challenge. This dissertation studies the basics of radiation hardening, essentials of clock design and impact of particle strikes on clocks in detail and presents design techniques for hardening complete clock systems in digital ICs. Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse clocked latches and physical design methodologies for using TMR master-slave flip-flops in application specific ICs (ASICs) are proposed. A novel temporal pulse clocked latch design for low power radiation hardened applications is also proposed. Techniques for designing custom RHBD clock distribution networks (clock spines) and ASIC clock trees for a radiation hardened microprocessor using standard CAD tools are presented. A framework for analyzing the vulnerabilities of clock trees in general, and study the parameters that contribute the most to the tree’s failure, including impact on controlled latches is provided. This is then used to design an integrated temporally redundant clock tree and pulse clocked flip-flop based clocking scheme that is robust to single event transients (SETs) and single event upsets (SEUs). Subsequently, designing robust clock delay lines for use in double data rate (DDRx) memory applications is studied in detail. Several modules of the proposed radiation hardened all-digital delay locked loop are designed and studied. Many of the circuits proposed in this entire body of work have been implemented and tested on a standard low-power 90-nm process. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

Os efeitos produzidos pela interação da radiação ionizante com os circuitos integrados podem ser classificados em efeitos de eventos únicos (Single Event Effects - SEE), comumente relacionados a problemas transientes, e efeitos de dose total ionizante (Total Ionization Dose - TID), os quais se originam em decorrência do longo tempo de exposição à radiação ionizante. Com relação à proteção desses circuitos, técnicas, como redundâncias temporais e espaciais, podem ser aplicadas a fim de reduzir a ocorrência de eventos transientes. Por outro lado, efeitos de TID e mesmo alguns SEE específicos, como os que causam degradações permanentes do circuito, podem ser atenuados drasticamente através de técnicas propostas em nível de layout. Nesse contexto, este trabalho analisa os conceitos básicos envolvidos na interação da radiação com o transistor MOS, desvios de suas características elétricas e técnicas de atenuação dos efeitos acumulativos aplicadas em níveis de arquitetura de sistemas, de processo de fabricação e de dispositivo. Contudo, este trabalho realiza uma abordagem mais detalhada de técnicas de tolerância em nível de layout. A tolerância em nível de layout do transistor é o resultado da combinação entre tecnologia escolhida agregada ao uso de anéis de guarda (guard rings) e aplicação de técnicas em nível de dispositivo como, por exemplo, a de geometria fechada (enclosed-gate). Este trabalho explora diferentes topologias de geometria fechada analisando diferentes modelagens e estimativas de razão de aspecto (W⁄L). Além disso, todas as análises e propostas apresentadas ao longo deste trabalho levam em conta o ambiente de projeto comercial, de forma que os dispositivos e técnicas propostas possam ser aplicadas e fabricadas utilizando ferramentas de projeto comerciais, respeitando restrições quando a dimensões e espaçamentos entre estruturas de acordo com requisitos comerciais de litografia. Os resultados obtidos corroboram o fato de que ao custo de área é possível que se obtenha um dispositivo mais tolerante à radiação e, neste caso, técnicas de mais alto nível ainda podem ser aplicadas de forma a atingir uma maior eficiência de proteção. / Studies related to ionizing radiation effects into MOS transistors are usually classified into two main groups, Single Event Effects (SEE) and Total Ionization Dose (TID). The former is related to transient effects and the later to the permanent effects which occurs during the whole lifetime of integrated circuits and devices. Architecture level for SEE mitigation techniques usually involves redundancy and majority voters, on the other hand, TID mitigation techniques act avoiding or reducing the weak and critical regions in the layout perspective. In this context this work proposes the analysis of primary physical mechanisms of radiation effects in semiconductor components and MOS transistors by exploring the electrical properties and related degradations. The mitigation (or hardening) techniques are explored not only at the architectural level but also by processes improvements. Nonetheless, this work is primarily focused to achieve a radiation hardened circuit by applying specific changes in the layout perspective making the design named as Radiation Hardened by Design (RHBD). Trading the area and circuit density it is possible to harden the most basic building block of electrical circuits (MOS transistors) and, in this case, by applying higher levels of mitigation techniques it is even possible to harden the entire circuit. Hardening by device is a combination of technology node, use of guard rings and techniques such as Enclosed Layout Transistor (ELT). Thus, this work realizes a comparative study of different proposed models to estimate the effective W/L aspect ratio in ELTs. Moreover, the analysis and approaches presented throughout this work take into account the commercial context, i.e., respecting the commercial Process Design Kits rules.

Os efeitos produzidos pela interação da radiação ionizante com os circuitos integrados podem ser classificados em efeitos de eventos únicos (Single Event Effects - SEE), comumente relacionados a problemas transientes, e efeitos de dose total ionizante (Total Ionization Dose - TID), os quais se originam em decorrência do longo tempo de exposição à radiação ionizante. Com relação à proteção desses circuitos, técnicas, como redundâncias temporais e espaciais, podem ser aplicadas a fim de reduzir a ocorrência de eventos transientes. Por outro lado, efeitos de TID e mesmo alguns SEE específicos, como os que causam degradações permanentes do circuito, podem ser atenuados drasticamente através de técnicas propostas em nível de layout. Nesse contexto, este trabalho analisa os conceitos básicos envolvidos na interação da radiação com o transistor MOS, desvios de suas características elétricas e técnicas de atenuação dos efeitos acumulativos aplicadas em níveis de arquitetura de sistemas, de processo de fabricação e de dispositivo. Contudo, este trabalho realiza uma abordagem mais detalhada de técnicas de tolerância em nível de layout. A tolerância em nível de layout do transistor é o resultado da combinação entre tecnologia escolhida agregada ao uso de anéis de guarda (guard rings) e aplicação de técnicas em nível de dispositivo como, por exemplo, a de geometria fechada (enclosed-gate). Este trabalho explora diferentes topologias de geometria fechada analisando diferentes modelagens e estimativas de razão de aspecto (W⁄L). Além disso, todas as análises e propostas apresentadas ao longo deste trabalho levam em conta o ambiente de projeto comercial, de forma que os dispositivos e técnicas propostas possam ser aplicadas e fabricadas utilizando ferramentas de projeto comerciais, respeitando restrições quando a dimensões e espaçamentos entre estruturas de acordo com requisitos comerciais de litografia. Os resultados obtidos corroboram o fato de que ao custo de área é possível que se obtenha um dispositivo mais tolerante à radiação e, neste caso, técnicas de mais alto nível ainda podem ser aplicadas de forma a atingir uma maior eficiência de proteção. / Studies related to ionizing radiation effects into MOS transistors are usually classified into two main groups, Single Event Effects (SEE) and Total Ionization Dose (TID). The former is related to transient effects and the later to the permanent effects which occurs during the whole lifetime of integrated circuits and devices. Architecture level for SEE mitigation techniques usually involves redundancy and majority voters, on the other hand, TID mitigation techniques act avoiding or reducing the weak and critical regions in the layout perspective. In this context this work proposes the analysis of primary physical mechanisms of radiation effects in semiconductor components and MOS transistors by exploring the electrical properties and related degradations. The mitigation (or hardening) techniques are explored not only at the architectural level but also by processes improvements. Nonetheless, this work is primarily focused to achieve a radiation hardened circuit by applying specific changes in the layout perspective making the design named as Radiation Hardened by Design (RHBD). Trading the area and circuit density it is possible to harden the most basic building block of electrical circuits (MOS transistors) and, in this case, by applying higher levels of mitigation techniques it is even possible to harden the entire circuit. Hardening by device is a combination of technology node, use of guard rings and techniques such as Enclosed Layout Transistor (ELT). Thus, this work realizes a comparative study of different proposed models to estimate the effective W/L aspect ratio in ELTs. Moreover, the analysis and approaches presented throughout this work take into account the commercial context, i.e., respecting the commercial Process Design Kits rules.

Os efeitos produzidos pela interação da radiação ionizante com os circuitos integrados podem ser classificados em efeitos de eventos únicos (Single Event Effects - SEE), comumente relacionados a problemas transientes, e efeitos de dose total ionizante (Total Ionization Dose - TID), os quais se originam em decorrência do longo tempo de exposição à radiação ionizante. Com relação à proteção desses circuitos, técnicas, como redundâncias temporais e espaciais, podem ser aplicadas a fim de reduzir a ocorrência de eventos transientes. Por outro lado, efeitos de TID e mesmo alguns SEE específicos, como os que causam degradações permanentes do circuito, podem ser atenuados drasticamente através de técnicas propostas em nível de layout. Nesse contexto, este trabalho analisa os conceitos básicos envolvidos na interação da radiação com o transistor MOS, desvios de suas características elétricas e técnicas de atenuação dos efeitos acumulativos aplicadas em níveis de arquitetura de sistemas, de processo de fabricação e de dispositivo. Contudo, este trabalho realiza uma abordagem mais detalhada de técnicas de tolerância em nível de layout. A tolerância em nível de layout do transistor é o resultado da combinação entre tecnologia escolhida agregada ao uso de anéis de guarda (guard rings) e aplicação de técnicas em nível de dispositivo como, por exemplo, a de geometria fechada (enclosed-gate). Este trabalho explora diferentes topologias de geometria fechada analisando diferentes modelagens e estimativas de razão de aspecto (W⁄L). Além disso, todas as análises e propostas apresentadas ao longo deste trabalho levam em conta o ambiente de projeto comercial, de forma que os dispositivos e técnicas propostas possam ser aplicadas e fabricadas utilizando ferramentas de projeto comerciais, respeitando restrições quando a dimensões e espaçamentos entre estruturas de acordo com requisitos comerciais de litografia. Os resultados obtidos corroboram o fato de que ao custo de área é possível que se obtenha um dispositivo mais tolerante à radiação e, neste caso, técnicas de mais alto nível ainda podem ser aplicadas de forma a atingir uma maior eficiência de proteção. / Studies related to ionizing radiation effects into MOS transistors are usually classified into two main groups, Single Event Effects (SEE) and Total Ionization Dose (TID). The former is related to transient effects and the later to the permanent effects which occurs during the whole lifetime of integrated circuits and devices. Architecture level for SEE mitigation techniques usually involves redundancy and majority voters, on the other hand, TID mitigation techniques act avoiding or reducing the weak and critical regions in the layout perspective. In this context this work proposes the analysis of primary physical mechanisms of radiation effects in semiconductor components and MOS transistors by exploring the electrical properties and related degradations. The mitigation (or hardening) techniques are explored not only at the architectural level but also by processes improvements. Nonetheless, this work is primarily focused to achieve a radiation hardened circuit by applying specific changes in the layout perspective making the design named as Radiation Hardened by Design (RHBD). Trading the area and circuit density it is possible to harden the most basic building block of electrical circuits (MOS transistors) and, in this case, by applying higher levels of mitigation techniques it is even possible to harden the entire circuit. Hardening by device is a combination of technology node, use of guard rings and techniques such as Enclosed Layout Transistor (ELT). Thus, this work realizes a comparative study of different proposed models to estimate the effective W/L aspect ratio in ELTs. Moreover, the analysis and approaches presented throughout this work take into account the commercial context, i.e., respecting the commercial Process Design Kits rules.

The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.

No description available.