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Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (p. 100-107).

A novel power-saving and small-area digital output cell is proposed in the first topic of this thesis. The new output cell dramatically reduces the output power consumption by filtering pre-defined spikes, which have been considered as one of the major power dissipation sources of the whole chip, with little sacrifice of speed or delay. The bound of the spikes to be removed can be pre-defined either dynamically by digital selection signals or permanently by fuses to be burned. The maximum operating clock is 200 MHz given a 10 pF off-chip load based on testing result of the testkey chip with an almost 28 % power reduction at all PVT corners. The second topic presents a design of a 19-T (19 transistors) full adder with high impedance circuit and conflict circuit. The transistor count is dramatically reduced such that the power dissipation as well as the area on chip is very small .

The main aim of a text-to-speech synthesis system is to convert ordinary text into an acoustic signal that is indistinguishable from human speech. This thesis presents an architecture to implement a concatenative speech synthesis algorithm targeted to FPGAs. Many current text-to-speech systems are based on the concatenation of acoustic units of recorded speech. Current concatenative speech synthesizers are capable of producing highly intelligible speech. However, the quality of speech often suffers from discontinuities between the acoustic units, due to contextual differences. This is the easiest method to produce synthetic speech. It concatenates prerecorded acoustic elements and forms a continuous speech element. The software implementation of the algorithm is performed in C whereas the hardware implementation is done in structural VHDL. A database of acoustic elements is formed first with recording sounds for different phones. The architecture is designed to concatenate acoustic elements corresponding to the phones that form the target word. Target word corresponds to the word that has to be synthesized. This architecture doesn't address the form discontinuities between the acoustic elements as its ultimate goal is the synthesis of speech. The Hardware implementation is verified on a Virtex (v800hq240-4) FPGA device.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references (p.60-63).

abstract: Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this thesis. Temporal hardening mitigates both SETs and SEUs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. This thesis presents an innovative, temporally hardened D flip-flop (TFF). The TFF physical design is laid out in the 130 nm TSMC process in the form of an interleaved multi-bit cell and the circuitry necessary for the flip-flop to be hardened against SETs and SEUs is analyzed with simulations verifying these claims. Comparisons are made to an unhardened D flip-flop through speed, size, and power consumption depicting how the RHBD technique used increases all three over an unhardened flip-flop. Finally, the blocks from both the hardened and the unhardened flip-flops being placed in Synthesis and auto-place and route (APR) design flows are compared through size and speed to show the effects of using the high density multi-bit layout. Finally, the TFF presented in this thesis is compared to two other flip-flops, the majority voter temporal/DICE flip-flop (MTDFF) and the C-element temporal/DICE flip-flop (CTDFF). These circuits are built on the same 130 nm TSMC process as the TFF and then analyzed by the same methods through speed, size, and power consumption and compared to the TFF and unhardened flip-flops. Simulations are completed on the MTDFF and CTDFF to show their strengths against D node SETs and SEUs as well as their weakness against CLK node SETs. Results show that the TFF is faster and harder than both the MTDFF and CTDFF. / Dissertation/Thesis / M.S. Electrical Engineering 2010

This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of "don't care" value. An approach for reducing the search space of the ATPG was introduced. The technique can significantly reduce the size of the search space but cannot ensure the completeness of the search. Results on ISCAS–85 benchmark circuits show that all of the proposed techniques allow for better fault detection in shorter amounts of time. These techniques, when used together, produced test vectors with high fault coverages. Also investigated in this thesis is the Decision Inversion Problem which threatens the completeness of ATPG tools such as HITEC or ATOMS. We propose a technique which can eliminate this problem by forcing the ATPG to consider search space with certain flip-flops untouched. Results show that our technique eliminated the decision inversion problem, ensuring the soundness of the search algorithm under the 9-valued logic model. / Master of Science

We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-optimal results, and finally a simulated annealing method that provides near optimal solutions with runtimes that meet our performance goals. The simulated annealing approach when applied on a ten benchmarks chosen from IWLS 93 benchmark suite, provides watermarking results with edge overhead of less than 6% on average with runtimes not exceeding five minutes.

Technology scaling to the nanometer levels has paved the way to realize multi-dimensional applications in a single product by increasing the density of the electronic devices on integrated chips. This has naturally attracted a wide variety of industries like medicine, communication, automobile, defense and even house-hold appliance, to use high speed multi-functional computing machines. Apart from the advantages of these nano-domain computing devices, their usage in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for comprehensive error analysis to enhance their reliability. Moreover, these nano-electronic devices have increased propensity to transient errors due to extremely small device dimensions and low switching energy. The nature of these transient errors is more probabilistic than deterministic, and so requires probabilistic models for estimation and analysis. In this dissertation, we present comprehensive analytic studies of error behavior in nano-level digital logic circuits using probabilistic reliability models. It comprises the design of exact probabilistic error models, to compute the maximum error over all possible input space in a circuit-specific manner; to study the behavior of transient errors in sequential circuits; and to achieve error mitigation through redundancy techniques. The model to compute maximum error, also provides the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. The model for sequential logic that can measure the expected output error probability, given a probabilistic input space, can account for both spatial dependencies and temporal correlations across the logic, using a time evolving causal network. For comprehensive error reduction in logic circuits, temporal, spatial and hybrid redundancy models, are implemented. The temporal redundancy model uses the triple temporal redundancy technique that applies redundancy in the input space, spatial redundancy model uses the cascaded triple modular redundancy technique that applies redundancy in the intermediate signal space and the hybrid redundancy techniques encapsulates both temporal and spatial redundancy schemes. All the above studies are performed on standard benchmark circuits from ISCAS and MCNC suites and the subsequent experimental results are obtained. These results clearly encompasses the various aspects of error behavior in nano VLSI circuits and also shows the efficiency and versatility of the probabilistic error models.

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